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| overview signal descriptions memory, operating modes, and interrupts external memory interface serial host interface serial audio interface general purpose i/o bootstrap code contents programming reference application examples index 1 2 3 4 6 7 5 i a b c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview signal descriptions memory, operating modes, and interrupts external memory interface serial host interface serial audio interface general purpose i/o bootstrap code contents programming reference application examples index 1 2 3 4 6 7 5 i a b c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56004 24-bit digital signal processor user? manual revision 1 motorola, incorporated semiconductor products sector dsp division f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6501 william cannon drive west austin, tx 78735-8598 this document (and other documents) can be viewed on the world wide web at http://www.motorola-dsp.com. this manual is one of a set of three documents. you need the following manuals to have complete product information: family manual, user? manual, and technical data. once ? is a trademark of motorola, inc. ? motorola inc., 1996 order this document by DSP56004UM/ad, rev. 1 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals? must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56011 user? manual -v the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . -vi dsp56011 user? manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual vii table of contents section 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.1 manual organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.2 manual conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2 dsp56004 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3 dsp56004 architectural overview . . . . . . . . . . . . . 1-8 1.3.1 memory and peripheral modules. . . . . . . . . . . . . . . . . . . . 1-9 1.3.2 dsp core processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.3.2.1 data arithmetic and logic unit (alu) . . . . . . . . . . . . . 1-10 1.3.2.2 address generation unit (agu) . . . . . . . . . . . . . . . . . 1-11 1.3.2.3 program control unit . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.3.2.4 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.2.5 address buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.2.6 phase lock loop (pll). . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.2.7 on-chip emulation (once) port . . . . . . . . . . . . . . . . . 1-12 1.3.3 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.3.3.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.3.3.2 x data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.3.3 y data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.3.4 bootstrap rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.3.5 external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.3.6 reserved memory spaces . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.4 input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.3.4.1 external memory interface . . . . . . . . . . . . . . . . . . . . . 1-17 1.3.4.2 serial host interface (shi) . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.4.3 serial audio interface (sai). . . . . . . . . . . . . . . . . . . . . 1-18 1.3.4.4 general purpose input/output . . . . . . . . . . . . . . . . . . 1-18 section 2 signal descriptions . . . . . . . . . . . . . . . . . . . . 2-1 2.1 signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . viii dsp56004 user? manual motorola 2.4 clock and pll signals . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5 external memory interface (emi) . . . . . . . . . . . . . . 2-7 2.6 interrupt and mode control . . . . . . . . . . . . . . . . . 2-10 2.7 serial host interface (shi) . . . . . . . . . . . . . . . . . . . 2-14 2.8 serial audio interface (sai) . . . . . . . . . . . . . . . . . . . 2-18 2.8.1 sai receiver section . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.8.2 sai transmitter section . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.9 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.10 on-chip emulation (once tm ) port . . . . . . . . . . . . . . 2-22 section 3 memory, operating modes, and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 dsp56004 program and data memory . . . . . . . . . . . 3-3 3.2.1 x data rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1.1 assembler routine to access the log 2 (x) table . . . . 3-5 3.2.1.2 assembler routine to access the 2 x table . . . . . . . . 3-5 3.2.2 y data rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.3 dsp56004 bootstrap rom . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.4 dsp56004rom bootstrap rom. . . . . . . . . . . . . . . . . . . . 3-6 3.2.5 program rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.6 reserved memory spaces . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.7 internal i/o memory map . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3 operating mode register (omr). . . . . . . . . . . . . . . . 3-9 3.3.1 dsp operating mode (mc, mb, ma)?its 4, 1, and 0. . . 3-9 3.3.2 stop delay (sd)?it 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.5 interrupt priority register. . . . . . . . . . . . . . . . . . 3-11 3.6 phase lock loop (pll) configuration . . . . . . . . . 3-15 3.7 hardware reset operation. . . . . . . . . . . . . . . . . . . 3-16 section 4 external memory interface. . . . . . . . . . . . 4-1 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.1 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.2 emi features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2 emi programming model . . . . . . . . . . . . . . . . . . . . . . . 4-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual ix 4.2.1 emi base address registers (ebar0 and ebar1) . . . . . 4-7 4.2.2 emi write offset register (ewor) . . . . . . . . . . . . . . . . . . 4-7 4.2.3 emi offset register (eor) . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.4 emi data write registers (edwr) . . . . . . . . . . . . . . . . . . 4-9 4.2.5 emi data read register (edrr) . . . . . . . . . . . . . . . . . . . 4-9 4.2.6 emi data register buffer (edrb) . . . . . . . . . . . . . . . . . . . 4-9 4.2.7 emi control/status register (ecsr) . . . . . . . . . . . . . . . . 4-10 4.2.7.1 emi data bus width (ebw)?it 0 . . . . . . . . . . . . . . . 4-10 4.2.7.2 emi word length (ewl[2:0])?its 16,2, and 1 . . . . . 4-11 4.2.7.3 emi addressing mode (eam[3:0])?its 6? . . . . . . . 4-12 4.2.7.4 emi increment ebar after read (einr)?it 7 . . . . . 4-16 4.2.7.5 emi increment ebar after write (einw)?it 8 . . . . 4-16 4.2.7.6 emi interrupt select (eis[1:0])?its 9?0 . . . . . . . . . 4-17 4.2.7.7 emi memory-wrap interrupt enable (emwie)?it 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.2.7.8 emi data write register empty (edwe)?it 12 . . . . 4-18 4.2.7.9 emi data read register full (edrf)?it 13 . . . . . . 4-18 4.2.7.10 emi data register buffer and data read register full (ebdf)?it 144-18 4.2.7.11 emi busy (ebsy)?it 15 . . . . . . . . . . . . . . . . . . . . . . 4-19 4.2.7.12 emi read trigger select (erts)?it 17 . . . . . . . . . . 4-19 4.2.7.13 emi dram memory timing (edtm)?it 18 . . . . . . . 4-19 4.2.7.14 emi sram memory timing (estm[3:0])?its 19?2 . . . . . . . . . . . . . . . . . . . . . . 4-20 4.2.7.15 emi enable (eme)?it 23 . . . . . . . . . . . . . . . . . . . . . 4-21 4.2.8 emi refresh control register (ercr) . . . . . . . . . . . . . . 4-21 4.2.8.1 emi refresh clock divider (ecd[7:0])?its 0? . . . . 4-22 4.2.8.2 ercr reserved bits?its 8?7, 21 . . . . . . . . . . . . . 4-22 4.2.8.3 emi refresh clock prescaler (eps[1:0])?its 18?9 4-22 4.2.8.4 emi one-shot refresh (eosr)?it 20 . . . . . . . . . . . 4-22 4.2.8.5 emi refresh enable when debugging (ered)?it 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.2.8.6 ercr refresh enable (eref)?it 23 . . . . . . . . . . . 4-23 4.3 emi address generation . . . . . . . . . . . . . . . . . . . . . . 4-23 4.3.1 sram absolute addressing . . . . . . . . . . . . . . . . . . . . . . 4-24 4.3.2 sram relative addressing . . . . . . . . . . . . . . . . . . . . . . . 4-25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x dsp56004 user? manual motorola 4.3.3 dram relative addressing. . . . . . . . . . . . . . . . . . . . . . . 4-27 4.3.4 dram absolute addressing . . . . . . . . . . . . . . . . . . . . . . 4-30 4.4 dram refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.4.1 dram refresh without using the internal refresh timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.4.2 dram refresh once port debug mode consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.4.3 using the internal refresh timer . . . . . . . . . . . . . . . . . . 4-33 4.4.3.1 ?n line?refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 4.4.3.2 ?ff line?refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4.4.3.3 once port debug mode consideration . . . . . . . . . . . 4-34 4.4.4 software controlled refresh . . . . . . . . . . . . . . . . . . . . . . 4-34 4.4.5 dram refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 4.5 emi operating considerations. . . . . . . . . . . . . . . . 4-38 4.5.1 emi triggering and pipelining . . . . . . . . . . . . . . . . . . . . . 4-38 4.5.2 read data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 4.5.3 write-data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 4.5.4 emi operation during stop . . . . . . . . . . . . . . . . . . . . . . . 4-45 4.5.5 emi operation during wait . . . . . . . . . . . . . . . . . . . . . . . 4-45 4.6 data-delay structure . . . . . . . . . . . . . . . . . . . . . . . . 4-46 4.7 emi-to-memory connection . . . . . . . . . . . . . . . . . . . 4-48 4.8 emi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 4.8.1 timing diagrams for dram addressing modes . . . . . . . 4-51 4.8.1.1 fast timing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 4.8.1.2 slow timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 4.8.2 timing diagrams for sram addressing modes . . . . . . . 4-64 section 5 serial host interface . . . . . . . . . . . . . . . . . . 5-1 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 serial host interface internal architecture . 5-4 5.3 serial host interface programming model. . . . 5-4 5.3.1 shi input/output shift register (iosr)?ost side . . . . . 5-7 5.3.2 shi host transmit data register (htx)?sp side . . . . 5-8 5.3.3 shi host receive data fifo (hrx)?sp side . . . . . . . 5-8 5.3.4 shi slave address register (hsar)?sp side . . . . . . . 5-9 5.3.4.1 hsar reserved bits?its 17?,19 . . . . . . . . . . . . . . 5-9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual xi 5.3.4.2 hsar i 2 c slave address (ha[6:3], ha1)?its 23?0,18 . . . . . . . . . . . . . . . . . . . 5-9 5.3.5 shi clock control register (hckr)?sp side . . . . . . . . 5-9 5.3.5.1 clock phase and polarity (cpha and cpol)?its 1? . . . . . . . . . . . . . . . . . . . . 5-9 5.3.5.2 hckr prescaler rate select (hrs)?it 2 . . . . . . . . 5-11 5.3.5.3 hckr divider modulus select (hdm[5:0])?its 8? . 5-11 5.3.5.4 hckr reserved bits?its 23?4, 11? . . . . . . . . . . 5-11 5.3.5.5 hckr filter mode (hfm[1:0]) ?bits 13?2 . . . . . . . 5-11 5.3.6 shi control/status register (hcsr)?sp side . . . . . . 5-13 5.3.6.1 hcsr host enable (hen)?it 0 . . . . . . . . . . . . . . . . 5-13 5.3.6.2 hcsr i 2 c/spi selection (hi2c)?it 1. . . . . . . . . . . . 5-13 5.3.6.3 hcsr serial host interface mode (hm[1:0])?its 3?. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.3.6.4 hcsr reserved bits?its 23, 18, 16, and 4 . . . . . . . 5-13 5.3.6.5 hcsr fifo-enable control (hfifo)?it 5. . . . . . . . 5-14 5.3.6.6 hcsr master mode (hmst)?it 6 . . . . . . . . . . . . . . 5-14 5.3.6.7 hcsr host request enable (hrqe[1:0])?its 8? . 5-14 5.3.6.8 hcsr idle (hidle)?it 9 . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.6.9 hcsr bus-error interrupt enable (hbie)?it 10 . . . 5-16 5.3.6.10 hcsr transmit-interrupt enable (htie)?it 11 . . . . 5-16 5.3.6.11 hcsr receive interrupt enable (hrie[1:0])?its 13?2 . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.6.12 hcsr host transmit underrun error (htue)?it 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.6.13 hcsr host transmit data empty (htde)?it 15. . . 5-17 5.3.6.14 host receive fifo not empty (hrne)?it 17 . . . . . 5-17 5.3.6.15 host receive fifo full (hrff)?it 19 . . . . . . . . . . . 5-18 5.3.6.16 host receive overrun error (hroe)?it 20 . . . . . . . 5-18 5.3.6.17 host bus error (hber)?it 21 . . . . . . . . . . . . . . . . . 5-18 5.3.6.18 hcsr host busy (hbusy)?it 22 . . . . . . . . . . . . . . 5-18 5.4 characteristics of the spi bus . . . . . . . . . . . . . . . 5-19 5.5 characteristics of the i 2 c bus. . . . . . . . . . . . . . . . 5-19 5.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.2 i 2 c data transfer formats . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.6 shi programming considerations . . . . . . . . . . . . . 5-22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xii dsp56004 user? manual motorola 5.6.1 spi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.6.2 spi master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.3 i 2 c slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.6.3.1 receive data in i 2 c slave mode . . . . . . . . . . . . . . . . 5-26 5.6.3.2 transmit data in i 2 c slave mode. . . . . . . . . . . . . . . . 5-27 5.6.4 i 2 c master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.6.4.1 receive data in i 2 c master mode . . . . . . . . . . . . . . . 5-29 5.6.4.2 transmit data in i 2 c master mode. . . . . . . . . . . . . . . 5-29 5.6.5 shi operation during stop . . . . . . . . . . . . . . . . . . . . . . . 5-30 section 6 serial audio interface . . . . . . . . . . . . . . . . . 6-1 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 serial audio interface internal architecture 6-4 6.2.1 baud-rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.2 receive section overview . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.3 sai transmit section overview . . . . . . . . . . . . . . . . . . . . 6-6 6.3 serial audio interface programming model . . . 6-8 6.3.1 baud rate control register (brc) . . . . . . . . . . . . . . . . . . 6-9 6.3.1.1 prescale modulus select (pm[7:0])?its 7? . . . . . . 6-10 6.3.1.2 prescaler range (psr)?it 8 . . . . . . . . . . . . . . . . . . 6-10 6.3.1.3 brc reserved bits?its 15? . . . . . . . . . . . . . . . . . 6-10 6.3.2 receiver control/status register (rcs). . . . . . . . . . . . . 6-10 6.3.2.1 rcs receiver 0 enable (r0en)?it 0 . . . . . . . . . . . 6-10 6.3.2.2 rcs receiver 1 enable (r1en)?it 1 . . . . . . . . . . . 6-11 6.3.2.3 rcs reserved bit?its 13 and 2 . . . . . . . . . . . . . . . 6-11 6.3.2.4 rcs receiver master (rmst)?it 3 . . . . . . . . . . . . 6-11 6.3.2.5 rcs receiver word length control (rwl[1:0])?its 4 and 5 . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.2.6 rcs receiver data shift direction (rdir)?it 6 . . . 6-12 6.3.2.7 rcs receiver left right selection (rlrs)?it 7. . . 6-12 6.3.2.8 rcs receiver clock polarity (rckp)?it 8 . . . . . . . 6-13 6.3.2.9 rcs receiver relative timing (rrel)?it 9 . . . . . . 6-13 6.3.2.10 rcs receiver data word truncation (rdwt)?it 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.2.11 rcs receiver interrupt enable (rxie)?it 11 . . . . . 6-15 6.3.2.12 rcs receiver interrupt location (rxil)?it 12 . . . . 6-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual xiii 6.3.2.13 rcs receiver left data full (rldf)?it 14 . . . . . . . 6-16 6.3.2.14 rcs receiver right data full (rrdf)?it 15 . . . . . 6-16 6.3.3 sai receive data registers (rx0 and rx1). . . . . . . . . . 6-17 6.3.4 transmitter control/status register (tcs) . . . . . . . . . . . 6-17 6.3.4.1 tcs transmitter 0 enable (t0en)?it 0 . . . . . . . . . . 6-17 6.3.4.2 tcs transmitter 1 enable (t1en)?it 1 . . . . . . . . . . 6-17 6.3.4.3 tcs transmitter 2 enable (t2en)?it 2 . . . . . . . . . . 6-18 6.3.4.4 tcs transmitter master (tmst)?it 3 . . . . . . . . . . . 6-18 6.3.4.5 tcs transmitter word length control (twl[1:0])?its 4 & 5 . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.3.4.6 tcs transmitter data shift direction (tdir)?it 6 . . 6-18 6.3.4.7 tcs transmitter left right selection (tlrs)?it 7 . 6-19 6.3.4.8 tcs transmitter clock polarity (tckp)?it 8 . . . . . . 6-19 6.3.4.9 tcs transmitter relative timing (trel)?it 9. . . . . 6-20 6.3.4.10 tcs transmitter data word expansion (tdwe)?it 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.3.4.11 tcs transmitter interrupt enable (txie)?it 11 . . . . 6-21 6.3.4.12 tcs transmitter interrupt location (txil)?it 12 . . . 6-22 6.3.4.13 tcs reserved bit?it 13. . . . . . . . . . . . . . . . . . . . . . 6-22 6.3.4.14 tcs transmitter left data empty (tlde)?it 14 . . . 6-22 6.3.4.15 tcs transmitter right data empty (trde)?it 15. . 6-23 6.3.5 sai transmit data registers (tx2, tx1 and tx0) . . . . . 6-23 6.4 programming considerations . . . . . . . . . . . . . . . . 6-24 6.4.1 sai operation during stop . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.4.2 initiating a transmit session . . . . . . . . . . . . . . . . . . . . . . 6-24 6.4.3 using a single interrupt to service both receiver and transmitter sections. . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.4.4 sai state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 section 7 general purpose input/output . . . . . . . . . 7-1 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 gpio programming model . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 gpio register (gpior) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3.1 gpior data bits (gd[3:0])?its 3? . . . . . . . . . . . . . . . . 7-4 7.3.2 gpior reserved bits?its 4?, 12?5, and 20?3 . . . . 7-4 7.3.3 gpior data direction bits (gdd[3:0])?its 11? . . . . . . 7-4 7.3.4 gpior control bits (gc[3:0])?its 19?6 . . . . . . . . . . . . 7-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xiv dsp56004 user? manual motorola appendix a bootstrap rom and data rom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1 dsp56004 bootstrap program. . . . . . . . . . . . . . . . . . a-3 a.2 assembler code to generate x data rom . . . . . . a-5 a.3 log 2 x table (x data rom) . . . . . . . . . . . . . . . . . . . . . . a-6 a.4 2 x table (x data rom). . . . . . . . . . . . . . . . . . . . . . . . . . . a-8 a.5 sine wave table (y data rom). . . . . . . . . . . . . . . . . . a-11 appendix b programming reference . . . . . . . . . . . . . . . b-1 b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 peripheral addresses. . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.3 interrupt addresses . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.4 interrupt priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.5 instruction set summary. . . . . . . . . . . . . . . . . . . . . . b-3 b.6 programming sheets . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 appendix c application examples . . . . . . . . . . . . . . . . . . c-1 c.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 c.2 typical system topology. . . . . . . . . . . . . . . . . . . . . . c-3 c.3 program overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-4 c.4 single delay line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-4 c.5 early reflection filter . . . . . . . . . . . . . . . . . . . . . . . c-5 c.6 two channel comb filter . . . . . . . . . . . . . . . . . . . . . . c-6 c.7 3-tap fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual xv list of figures figure 1-1 dsp56004 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 figure 2-1 dsp56004 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 3-1 dsp56004 internal memory map?ode 0. . . . . . . . . . . . . . . . . 3-4 figure 3-2 dsp56004rom internal memory map?ode 0 . . . . . . . . . . . . 3-4 figure 3-3 operating mode register (omr). . . . . . . . . . . . . . . . . . . . . . . . . 3-9 figure 3-4 interrupt priority register (address x:$ffff). . . . . . . . . . . . . . 3-12 figure 3-5 pll configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 figure 4-1 emi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 figure 4-2 emi control/status register (ecsr). . . . . . . . . . . . . . . . . . . . . . 4-8 figure 4-3 emi refresh control register (ercr) . . . . . . . . . . . . . . . . . . . 4-21 figure 4-4 emi address generation block diagram. . . . . . . . . . . . . . . . . . 4-23 figure 4-5 refresh timer functional diagram.. . . . . . . . . . . . . . . . . . . . . . 4-33 figure 4-6 timing diagram of a dram refresh cycle (fast). . . . . . . . . . . 4-37 figure 4-7 timing diagram of a dram refresh cycle (slow) . . . . . . . . . . 4-37 figure 4-8 emi pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 figure 4-9 illustration of the data-delay structure . . . . . . . . . . . . . . . . . . . 4-46 figure 4-10 dram for data delay buffers and for sram for bootstrap . . . 4-48 figure 4-11 sram for data delay buffers and for bootstrap . . . . . . . . . . . . 4-49 figure 4-12 replacing drams with srams for large arrays . . . . . . . . . . . 4-50 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xvi dsp56004 user? manual motorola figure 4-13 fast read or write dram access timing? . . . . . . . . . . . . . . 4-52 figure 4-14 fast read or write dram access timing? . . . . . . . . . . . . . . 4-53 figure 4-15 fast read or write dram access timing? . . . . . . . . . . . . . . 4-54 figure 4-16 fast read or write dram access timing? . . . . . . . . . . . . . . 4-55 figure 4-17 fast read or write dram access timing? . . . . . . . . . . . . . . 4-56 figure 4-18 fast read or write dram access timing? . . . . . . . . . . . . . . 4-57 figure 4-19 slow read or write dram access timing?. . . . . . . . . . . . . . 4-58 figure 4-20 slow read or write dram access timing?. . . . . . . . . . . . . . 4-59 figure 4-21 slow read or write dram access timing?. . . . . . . . . . . . . . 4-60 figure 4-22 slow read or write dram access timing?. . . . . . . . . . . . . . 4-61 figure 4-23 slow read or write dram access timing?. . . . . . . . . . . . . . 4-62 figure 4-24 slow read or write dram access timing?. . . . . . . . . . . . . . 4-63 figure 4-25 sram read/write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64 figure 5-1 serial host interface block diagram . . . . . . . . . . . . . . . . . . . . . . 5-5 figure 5-2 shi clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 figure 5-3 shi programming model?ost side. . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-4 shi programming model?sp side. . . . . . . . . . . . . . . . . . . . . . 5-7 figure 5-5 shi i/o shift register (iosr). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-6 spi data-to-clock timing diagram . . . . . . . . . . . . . . . . . . . . . . 5-11 figure 5-7 i 2 c bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 figure 5-8 i 2 c start and stop events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 figure 5-9 acknowledgment on the i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . 5-22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual xvii figure 5-10 i 2 c bus protocol for host write cycle . . . . . . . . . . . . . . . . . . . 5-23 figure 5-11 i 2 c bus protocol for host read cycle . . . . . . . . . . . . . . . . . . . 5-23 figure 6-1 sai baud-rate generator block diagram . . . . . . . . . . . . . . . . . . 6-4 figure 6-2 sai receive section block diagram . . . . . . . . . . . . . . . . . . . . . . 6-5 figure 6-3 sai transmit section block diagram . . . . . . . . . . . . . . . . . . . . . 6-7 figure 6-4 sai registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 figure 6-5 receiver data shift direction (rdir) programming . . . . . . . . . 6-12 figure 6-6 receiver left/right selection (rlrs) programming. . . . . . . . . 6-12 figure 6-7 receiver clock polarity (rckp) programming . . . . . . . . . . . . . 6-13 figure 6-8 receiver relative timing (rrel) programming . . . . . . . . . . . . 6-14 figure 6-9 receiver data word truncation (rdwt) programming . . . . . . 6-14 figure 6-10 transmitter data shift direction (tdir) programming . . . . . . . 6-19 figure 6-11 transmitter left/right selection (tlrs) programming . . . . . . . 6-19 figure 6-12 transmitter clock polarity (tckp) programming . . . . . . . . . . . 6-20 figure 6-13 transmitter relative timing (trel) programming . . . . . . . . . . 6-20 figure 6-14 transmitter data word expansion (tdwe) programming . . . . 6-21 figure 7-1 gpio control/data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 figure 7-2 gpio circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 figure b-1 on-chip peripheral memory map. . . . . . . . . . . . . . . . . . . . . . . . . b-4 figure b-2 status register (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-14 figure b-3 interrupt priority register (ipr) . . . . . . . . . . . . . . . . . . . . . . . . . b-15 figure b-4 operating mode register (omr). . . . . . . . . . . . . . . . . . . . . . . . b-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xviii dsp56004 user? manual motorola figure b-5 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . b-17 figure b-6 emi control/status register (ecsr) . . . . . . . . . . . . . . . . . . . . . b-18 figure b-7 emi base address and offset registers . . . . . . . . . . . . . . . . . . b-19 figure b-8 emi data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-20 figure b-9 emi refresh control register (ercr). . . . . . . . . . . . . . . . . . . . b-21 figure b-10 shi slave address and clock control registers . . . . . . . . . . . . b-22 figure b-11 shi host data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-23 figure b-12 shi control/status register (hcsr) . . . . . . . . . . . . . . . . . . . . . b-24 figure b-13 sai receiver control/status register (rcs) . . . . . . . . . . . . . . . b-25 figure b-14 sai transmitter control/status register (tcs) . . . . . . . . . . . . . b-26 figure b-15 sai baud rate control and receive data registers . . . . . . . . . b-27 figure b-16 sai transmit data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . b-28 figure b-17 gpio control/data register (gpior) . . . . . . . . . . . . . . . . . . . . b-29 figure c-1 topology of dsp typical audio application . . . . . . . . . . . . . . . . . c-3 figure c-2 using the dsp56004 for surround sound . . . . . . . . . . . . . . . . . . c-4 figure c-3 single delay line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-6 figure c-4 two-channel comb filter structure. . . . . . . . . . . . . . . . . . . . . . . c-9 figure c-5 3 tap fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual xix list of tables table 1-1 high true / low true signal conventions. . . . . . . . . . . . . . . . . . 1-6 table 1-2 interrupt starting addresses and sources. . . . . . . . . . . . . . . . . 1-13 table 1-3 on-chip peripheral memory map. . . . . . . . . . . . . . . . . . . . . . . . 1-16 table 2-1 dsp56004 functional group signal allocations . . . . . . . . . . . . . 2-3 table 2-2 power inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-3 grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-4 clock and pll signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-5 external memory interface (emi) signals . . . . . . . . . . . . . . . . . . 2-7 table 2-6 emi operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 table 2-7 interrupt and mode control signals. . . . . . . . . . . . . . . . . . . . . . 2-10 table 2-8 serial host interface (shi) signals . . . . . . . . . . . . . . . . . . . . . . 2-14 table 2-9 serial audio interface (sai) receiver signals . . . . . . . . . . . . . . 2-18 table 2-10 serial audio interface (sai) transmitter signals . . . . . . . . . . . . 2-20 table 2-11 general purpose i/o (gpio) signals . . . . . . . . . . . . . . . . . . . . 2-21 table 2-12 on-chip emulation port signals . . . . . . . . . . . . . . . . . . . . . . . . 2-22 table 3-1 memory configurations (word width is 24 bits). . . . . . . . . . . . . . 3-3 table 3-2 internal i/o memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 table 3-3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 table 3-4 interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xx dsp56004 user? manual motorola table 3-5 interrupt vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 table 4-1 emi interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-2 emi internal interrupt priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-3 emi memory accesses and locations per word . . . . . . . . . . . . 4-10 table 4-4 emi word length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 table 4-5 emi addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 table 4-6 emi maximum sram size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 table 4-7 emi maximum dram size (relative addressing) . . . . . . . . . . . 4-14 table 4-8 emi maximum dram size (absolute addressing) . . . . . . . . . . 4-15 table 4-9 emi read/write interrupt select. . . . . . . . . . . . . . . . . . . . . . . . . 4-17 table 4-10 emi dram timing (clock cycles per word transfer). . . . . . . . . . 4-19 table 4-11 emi sram timing (clock cycles per word transfer) . . . . . . . . . . 4-20 table 4-12 relative addressing extension bits . . . . . . . . . . . . . . . . . . . . . . 4-24 table 4-13 word address to physical address mapping for sram. . . . . . . 4-26 table 4-14 word-address-to-physical-address mapping for dram . . . . . . 4-28 table 4-15 address generation for dram relative addressing . . . . . . . . 4-29 table 4-16 word-to-physical-address mapping for dram absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 table 4-17 typical dram refresh timing requirements . . . . . . . . . . . . . . 4-35 table 4-18 continuous refresh: timings and settings for eps[1:0] and ecd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 table 4-19 burst refresh: timings and settings for eps[1:0] and ecd[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual xxi table 4-20 maximum dsp clock frequencies when using dram . . . . . . 4-50 table 4-21 maximum dsp clock frequencies when using sram . . . . . . 4-51 table 4-22 maximum dsp clock frequencies when using eprom . . . . . 4-51 table 5-1 shi interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 table 5-2 shi internal exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 table 5-3 shi noise reduction filter mode . . . . . . . . . . . . . . . . . . . . . . . 5-12 table 5-4 shi data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 table 5-5 hreq function in shi slave modes. . . . . . . . . . . . . . . . . . . . . 5-15 table 5-6 hcsr receive interrupt enable bits. . . . . . . . . . . . . . . . . . . . . 5-17 table 6-1 sai interrupt vector locations. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 table 6-2 sai internal interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 table 6-3 receiver word length control . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 table 6-4 transmitter word length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 table 7-1 gpio pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 table b-1 interrupt starting addresses and sources. . . . . . . . . . . . . . . . . . b-5 table b-2 interrupt priorities within an ipl . . . . . . . . . . . . . . . . . . . . . . . . . b-6 table b-3 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual 1-1 section 1 overview f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview motorola dsp56004 user? manual 1-2 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 dsp56004 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3 dsp56004 architectural overview . . . . . . . . . . . . . 1-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-3 dsp56004 user? manual motorola overview introduction 1.1 introduction this manual describes in detail the dsp56004 24-bit digital signal processor (dsp), its memory, operating modes, and peripheral modules. this manual is intended to be used with the dsp56000 family manual (dsp56kfamum/ad) and the dsp56004 technical data sheet (dsp56004/d). the family manual describes the central processing unit (cpu), programming models, and the instruction set. the data sheet provides electrical specifications, timing, pinouts, and packaging descriptions. these documents, as well as motorola? dsp development tools, can be obtained through a local motorola semiconductor sales office or authorized distributor. to receive the latest information, access the motorola dsp home page located at http://www.motorola-dsp.com the dsp56004 is a general purpose dsp designed for audio and sound effects applications. it is based on the dsp56000 core architecture and implemented in the same scalable technology as the dsp56002, dsp56005, dsp56007, and other 24-bit dsp56000 modular products. this dsp is available in two versions: the dsp56004 and the dsp56004rom. the two devices are identical in every way, except for their memory configuration; specifically, the amount of rom and ram available differs between the two devices (see section 3, memory, operating modes, and interrupts ). also, the programs stored in rom are not the same on the two variants (see appendix a, bootstrap and rom code listings ). the dsp56004 also provides the following on-chip peripherals to support audio processing functions: external memory interface (emi) ?interfaces dram, sram, and eprom; the dram interface is specifically designed to provide access to a large, inexpensive memory space, such as that required by many audio applications serial host interface (shi) ?imple communications and control interface between a host processor and the dsp serial audio interface (sai) ?ser-programmable interface that provides support for a wide variety of serial audio formats to support a number of standard audio devices dedicated general purpose input/output (gpio) signals ?four additional individually controlled input or output signals the dsp56004 has the power and ease-of-programming required for stand-alone, embedded applications. the versatile, on-board peripherals allow the dsp to be easily connected to almost any other processor with little or no additional logic. the low pin-count (80 pins) allows the dsp56004 to be available in a small, inexpensive package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview introduction motorola dsp56004 user? manual 1-4 1.1.1 manual organization this manual includes the following sections: section 1?verview furnishes an description of the manual organization and provides a brief description of the dsp56004. section 2?ignal descriptions describes the dsp56004 signals and signal groupings. section 3?emory, operating modes, and interrupts describes the internal memory organization, operating modes, interrupt processing, and chip initialization during hardware reset. section 4?xternal memory interface describes the external memory interface (emi) port (port a), its registers, and its controls. section 5?erial host interface describes the operation, registers, and control of the serial host interface (shi). section 6?erial audio interface describes the operation of the serial audio interface (sai), its registers, and its controls. section 7?eneral purpose i/o describes the four dedicated general purpose input/output (gpio) pins, the gpio registers, and gpio control. appendix a?ootstrap code listings lists the code used to bootstrap the dsp56004. appendix b?rogramming reference provides a quick reference for the instructions and registers used by the dsp56004. these sheets are provided with the expectation that they be photocopied and used by programmers when programming the registers. appendix c?pplication examples provides a selection of typical circuit block diagrams and coding examples. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-5 dsp56004 user? manual motorola overview introduction 1.1.2 manual conventions the following conventions are used in this manual: the word ?eset?is used in three different contexts in this manual. there is a reset pin that is always written as ?eset ,?there is a reset instruction that is always written as ?eset? and the word reset, used to refer to the reset function, is written in lower case (with a leading capital letter as grammar dictates.) bits within a register are indicated aa[n:0] when more than one bit is involved in a description. for purposes of description, the bits are presented as if they are contiguous within the register; however, this is not always the case. refer to the programming model diagrams or to the programming sheets to see the exact location of bits within a register. when a bit is described as ?et,?its value is 1. when a bit is described as ?leared,?its value is 0. hex (hexadecimal) values are indicated with a dollar sign ($) preceding the hex value, as in ?fffb is the x memory address for the interrupt priority register (ipr). code examples are displayed in a monospaced font, as shown in example 1-1 . pins or signals listed in code examples that are asserted low have a tilde (~) in front of their names. the word ?ssert?means that a high true (active high) signal is pulled high (to v cc ) or that a low true (active low) signal is pulled low (to ground). the word ?eassert?means that a high true signal is pulled low (to ground) or that a low true signal is pulled high (to v cc ). overbars are used to indicate a signal that is active when pulled to ground (see table 1-1 ). for example, the reset pin is active when pulled to ground. therefore, references to the reset pin will always have an overbar. such pins and signals are also said to be ?ctive low?or ?ow true. example 1-1 sample code listing movep #0,x:eor0 ; drive 2nd read trigger bset #erts,x:ecsr ; set read triggers by reading eddr do #(n-2),end_ol ; loop to drive more (n-2) triggers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview dsp56004 features motorola dsp56004 user? manual 1-6 1.2 dsp56004 features the dsp56004 consists of the dsp56000 core, program and data memory, and peripherals useful for embedded control applications. the following paragraphs provide a list of dsp56004 features and a brief description of its core and peripheral components. general features harvard architecture, with four 24-bit internal data buses and three 16-bit internal address buses, permitting simultaneous accesses to program memory and two data memories software-programmable, phase lock loop (pll) frequency synthesizer for the core clock with a wide range of frequency multiplications (1 to 4096) and power-saving clock divider (2 i , where i = 0 to 15) for reduced clock noise on-chip emulation (once ? ) port for unobtrusive, comprehensive, processor speed-independent hardware/software debugging stop and wait low-power standby modes efficient, object code compatible, 24-bit 56000-family dsp engine on-chip peripheral registers memory-mapped in data memory space table 1-1 high true / low true signal conventions signal/symbol logic state signal state voltage pin 1 true asserted v cc 3 pin 1 false deasserted ground 2 pin 1 true asserted ground 2 pin 1 false deasserted v cc 3 note: 1. pin is a generic term for any pin on the device. 2. ground is an acceptable low voltage level. see the appropriate data sheet for the range of acceptable low voltage levels (typically a ttl logic low). 3. v cc is an acceptable high voltage level. see the appropriate data sheet for the range of acceptable high voltage levels (typically a ttl logic high). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-7 dsp56004 user? manual motorola overview dsp56004 features three external interrupt request pins data arithmetic logic unit (data alu), program control unit (pcu), and address generation unit (agu) all integral to the core processor bootstrap loading from shi or emi (in absolute sram mode) completely pin-compatible with dsp56004 and dsp56007 for easy upgrades fully static, hcmos design for operating frequencies from maximum specified operating frequency down to dc 80-pin plastic quad flat pack surface-mount package; 14 14 2.45 mm; 0.65 mm lead pitch highly parallel instruction set with unique dsp addressing modes two 56-bit accumulators, including extension byte parallel 24 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) double precision 48 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle fractional and integer arithmetic with support for multiprecision arithmetic hardware support for block-floating point fast fourier transforms (ffts) zero-overhead fast interrupts (2 instruction cycles) nested hardware do loops on-chip memory modules (refer to section 3 for detailed information) peripheral modules: external memory interface (emi), implemented as a peripheral, supporting: direct connection of page-mode drams: 64 k 4 bits, 64 k 8 bits, 256 k 4 bits, 256 k 8 bits, 1 m 4 bits, 1 m 8 bits, 4 m 4 bits, and 4 m 8 bits srams (one to four): 256 k 8 bits bootstrap from eprom data bus may be 4 or 8 bits wide f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview dsp56004 architectural overview motorola dsp56004 user? manual 1-8 data words may be 8, 12, 16, 20, or 24 bits wide serial host interface (shi): spi and i 2 c protocols, single master capability, 10-word receive fifo register, support for 8-, 16-, and 24-bit words serial audio interface (sai) includes two receivers and three transmitters, master or slave capability, and implementation of philips, sony, and matsushita audio protocols; two complete sets of sai interrupt vectors four independent, programmable gpio lines 1.3 dsp56004 architectural overview the dsp56004 is a member of the 24-bit dsp56000 family. the dsp is composed of the 24-bit dsp56000 core, memory, and a set of peripheral modules, as shown in figure 1-1 on page 1-9. the 24-bit dsp56000 core is composed of a data alu, an address generation unit (agu), a program control unit (pcu), an on-chip emulation (once ) port, and a pll designed to allow the dsp to run at full speed while using a low-speed clock. the dsp56000-family architecture, upon which the dsp56004 is built, was designed to maximize throughput in data-intensive digital signal processing applications. the result is a dual-natured, expandable architecture with sophisticated on-chip peripherals and versatile gpio. the dsp56000 core is dual-natured in that there are two independent, expandable data memory spaces, two address arithmetic units, and a data alu that has two accumulators and two shifter/limiters. the duality of the architecture makes it easier to write software for dsp applications. for example, data is naturally partitioned into coefficient and data spaces for filtering and transformations, and into real and imaginary spaces for performing complex arithmetic. the dsp56000 architecture is especially suited for audio applications since its arithmetic operations are executed on 24-bit or 48-bit data words. this is a significant advantage for audio over 16-bit and 32-bit architectures: 16-bit dsp architectures have insufficient precision for cd-quality sound, and while 32-bit dsp architectures possess the necessary precision, with extra silicon and cost overhead they are not suitable for high-volume, cost-driven audio applications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-9 dsp56004 user? manual motorola overview dsp56004 architectural overview 1.3.1 memory and peripheral modules the following memory and peripheral modules are included on the dsp56004: external memory interface (emi) ?he emi provides simple connection to external dram and/or sram and/or eprom memories. this memory interface is designed to provide a simple and inexpensive connection to large dram memories (up to two 4 m 4 bits) for audio delay lines. the port is configurable as either 4 or 8 bits wide, providing a convenient interface to standard dram, eprom, and sram parts. data word packing/unpacking is automatic to simplify and accelerate converting between memory word size and data word size. absolute addressing can be used for random memory access, program bootstrap, overlays, and to access external peripherals. relative addressing, assisted by base-offset registers, can easily be used to set up delay lines. figure 1-1 dsp56004 block diagram y data memory x data memory program memory program control unit 24-bit dsp56000 core once tm port pll clock gen. 4 9 5 29 16-bit bus 24-bit bus data alu 24 24 + 56 ? 56-bit mac two 56-bit accumulators interrupt control program decode controller program address generator 4 irqa , irqb 4 3 internal data bus switch address generation unit nmi , reset pab xab yab gdb pdb xdb ydb general purpose i/o (gpio) external memory interface (emi) serial audio interface (sai) serial host interface (shi) aa0248k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview dsp56004 architectural overview motorola dsp56004 user? manual 1-10 serial host interface (shi) ?he shi provides a fast, yet simple serial interface to connect the dsp56004 to a host processor or to another serial peripheral device. two serial protocols are available: the motorola serial peripheral interface (spi) bus and the philips inter integrated-circuit control (i 2 c) bus. the shi will operate with 8-, 16-, and 24-bit words and the receiver has an optimal 10-word fifo register to reduce the receive interrupt rate. serial audio interface (sai) ?he sai provides a synchronous serial interface that allows the dsp56004 to communicate using a wide range of standard serial data formats used by audio manufacturers at bit rates up to one-third the dsp core clock rate (e.g., 27 mhz for a 81 mhz clock). there are three synchronized data transmission lines and two synchronized data reception lines, all of which are double-buffered. general purpose input/output (gpio) ?he gpio has four dedicated signals that can be independently programmed to be inputs, standard ttl outputs, open collector outputs, or disconnected. 1.3.2 dsp core processor the 24-bit dsp56000 core is composed of a data alu, an agu, a pc, and the buses that connect them together. the once port and a pll are integral parts of this processor. figure 1-1 on page 1-9 illustrates the dsp block diagram, showing the components of the core processor, as well as the peripherals specific to the dsp56004. the following paragraphs present a brief overview of the dsp56000 core processor. for more thorough detail, refer to the dsp56000 family manual . 1.3.2.1 data arithmetic and logic unit (data alu) the data arithmetic and logic unit (alu) has been designed to be fast and provide the capability to process signals having a wide dynamic range. special circuitry has been provided to facilitate the processing of data overflows and round-off errors. the data alu performs all of the arithmetic and logical operations on data operands. the data alu consists of four 24-bit input registers, two 48-bit accumulator registers (also usable as four 24-bit accumulators), two 8-bit accumulator extension registers, an accumulator shifter, two data shifter/limiters, and a parallel single-cycle non-pipelined multiplier-accumulator (mac). data alu operations use fractional two?-complement arithmetic. data alu registers may be read or written over the x data bus (xdb) and y data bus (ydb) as 24- or 48-bit operands. the 24-bit data words provide 144 db of dynamic range. this is sufficient for most real-world applications, including high-quality audio applications, since the majority of analog-to-digital (a/d) and digital-to-analog (d/a) converters are 16 bits or less, and certainly not greater than 24 bits. the 56-bit accumulation internal to the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-11 dsp56004 user? manual motorola overview dsp56004 architectural overview data alu provides 336 db of internal dynamic range, assuring no loss of precision due to intermediate processing. two data shifter/limiters provide special post-processing on data reads (from the data alu accumulator registers and directed to the xdb or ydb). the data shifters are capable of shifting data one bit to the left or to the right, as well as passing the data unshifted. each data shifter has a 24-bit output with overflow indication. the data shifters are controlled by scaling-mode bits. these shifters permit no-overhead dynamic scaling of fixed point data by simply programming the scaling mode bits. this permits block floating-point algorithms to be implemented efficiently. for example, fast fourier transform (fft) routines can use this feature to selectively scale each butterfly pass. saturation arithmetic is accommodated to minimize errors due to overflow. overflow occurs when a source operand requires more bits for accurate representation than there are available in the destination. to minimize the error due to overflow, ?imiting?causes the maximum (or minimum, if negative) value to be written to the destination with an error flag. 1.3.2.2 address generation unit (agu) the address generation unit (agu) performs all address storage and effective address calculations necessary to access data operands in memory. it implements three types of arithmetic to update addresses linear, modulo, and reverse carry. this unit operates in parallel with other chip resources to minimize address generation overhead. the agu contains eight address registers r0?7 (i.e., rn), eight offset registers n0?7 (i.e., nn), and eight modifier registers m0?7 (i.e., mn). the rn registers are 16-bit registers that may contain an address or data. each rn register may provide addresses to the x memory address bus (xab), y memory address bus (yab), and the program address bus (pab). the nn and mn registers are 16-bit registers that are normally used to update the rn registers, but may be used for data. agu registers may be read from or written to via the global data bus as 16-bit operands. the agu has two modulo arithmetic units that can generate two independent 16-bit addresses every instruction cycle for any two of the xab, yab, or pab. 1.3.2.3 program control unit (pcu) the program control unit (pcu) performs instruction prefetch, instruction decoding, hardware do loop control, and exception processing. it contains six directly addressable registers the program counter (pc), loop address (la), loop counter (lc), status register (sr), operating mode register (omr), and stack pointer (sp). the pcu also contains a 15 level by 32-bit system stack memory. the 16-bit pc can address 65,536 (64 k) locations in program memory space. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview dsp56004 architectural overview motorola dsp56004 user? manual 1-12 1.3.2.4 data buses data movement on the chip occurs over four bidirectional 24-bit buses?he x data bus (xdb), the y data bus (ydb), the program data bus (pdb), and the global data bus (gdb). certain instructions concatenate xdb and ydb to form a 48-bit data bus. data transfers between the data alu and the two data memories, x and y, occur over the xdb and ydb, respectively. these transfers can occur simultaneously on the dsp, maximizing data throughput. all other data transfers, such as i/o transfers to internal peripherals, occur over the gdb. instruction word pre-fetches take place over the pdb in parallel with data transfers. transfers between buses are accomplished through the internal bus switch. 1.3.2.5 address buses addresses are specified for internal x data memory and y data memory using two unidirectional 16-bit buses?he x address bus (xab) and the y address bus (yab). program memory addresses are specified using the 16-bit program address bus (pab). 1.3.2.6 phase lock loop (pll) the phase lock loop (pll) reduces the need for multiple oscillators in a system design, thus reducing the overall system cost. an additional benefit of the pll is that it permits the use of a low-frequency external clock with no sacrifice of processing speed. the pll converts the low-frequency external clock to the high speed internal clock needed to run the dsp at maximum speed. this diminishes the electromagnetic interference generated by high frequency clocking. the pll performs frequency multiplication to allow the processor to use almost any available external system clock for full-speed operation. it also improves the synchronous timing of the processor? external memory port, significantly reducing the timing skew between extal and the internal chip phases when the multiplication factor (mf) 4. the pll is unique in that it provides a low power divider on its output, which can reduce or restore the chip operating frequency without losing the pll lock. 1.3.2.7 on-chip emulation (once) port the on-chip emulation (once ) port provides a sophisticated debugging tool that allows simple, inexpensive, and speed-independent access to the processor? internal registers and peripherals. the once port tells the application programmer the exact status of most of the on-chip registers, memory locations, and buses, as well as storing the addresses of the last five instructions that were executed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-13 dsp56004 user? manual motorola overview dsp56004 architectural overview 1.3.3 memories the three independent memory spaces of the dsp56004? data, y data, and program?nd their configurations are discussed briefly here. see section 3 , memory, operating modes, and interrupts for more detail . 1.3.3.1 program memory the on-chip program memory is 24-bits wide. addresses are received from the pcu (usually from the program counter) over the program address bus (pab). program memory may be written using movem instructions. the interrupt vectors are located in the bottom 128 locations of program memory. table 1-2 lists the interrupt vector addresses and indicates the interrupt priority level (ipl) of each interrupt source. program ram has many advantages. it provides a means to develop code efficiently. programs can be changed dynamically, allowing efficient overlaying of dsp software algorithms. in this way the on-chip program ram operates as a fixed cache, thereby minimizing accesses to slower external memory. the bootstrap mode, described in appendix a, provides a convenient, low-cost method to load the dsp56004 program ram from a single, inexpensive eprom connected to the emi, or through the shi, using either spi or i 2 c formats, after a power-on reset. table 1-2 interrupt starting addresses and sources interrupt starting address ipl interrupt source p:$0000 3 hardware reset p:$0002 3 stack error p:$0004 3 trace p:$0006 3 swi p:$0008 0? irqa p:$000a 0? irqb p:$000c reserved p:$000e reserved p:$0010 0? sai left channel transmitter if txil = 0 p:$0012 0? sai right channel transmitter if txil = 0 p:$0014 0? sai transmitter exception if txil = 0 p:$0016 0? sai left channel receiver if rxil = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview dsp56004 architectural overview motorola dsp56004 user? manual 1-14 p:$0018 0? sai right channel receiver if rxil = 0 p:$001a 0? sai receiver exception if rxil = 0 p:$001c reserved p:$001e 3 nmi p:$0020 0? shi transmit data p:$0022 0? shi transmit underrun error p:$0024 0? shi receive fifo not empty p:$0026 reserved p:$0028 0? shi receive fifo full p:$002a 0? shi receive overrun error p:$002c 0? shi bus error p:$002e reserved p:$0030 0? emi write data p:$0032 0? emi read data p:$0034 0? emi ebar0 memory wrap p:$0036 0? emi ebar1 memory wrap p:$0038 reserved p:$003a reserved p:$003c reserved p:$003e 3 illegal instruction p: $0040 0? sai left channel transmitter if txil = 1 p: $0042 0? sai right channel transmitter if txil = 1 p: $0044 0? sai transmitter exception if txil = 1 p: $0046 0? sai left channel receiver if rxil = 1 p: $0048 0? sai right channel receiver if rxil = 1 p: $004a 0? sai receiver exception if rxil = 1 p: $004c reserved : : p: $007e reserved table 1-2 interrupt starting addresses and sources (continued) interrupt starting address ipl interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-15 dsp56004 user? manual motorola overview dsp56004 architectural overview 1.3.3.2 x data memory the on-chip x data memory is 24 bits wide. addresses are received from the xab, and data transfers to the data alu occur on the xdb. 1.3.3.3 y data memory the on-chip y data memory is 24 bits wide. addresses are received from the yab, and data transfers to the data alu occur on the ydb. 1.3.3.4 bootstrap rom the bootstrap rom occupies locations 0?1 ($0?1f) and 256?87 ($100?11f) in two areas in the memory map on the dsp56004. the bootstrap rom is factory-programmed to perform the bootstrap operation following hardware reset; it either jumps to the user? rom starting address (p:$2000) or downloads up to 512 words of user program from either the emi port or the shi port (in spi or i 2 c format). the bootstrap rom activity is controlled by the bits ma, mb, and mc, which are located in the omr. when in the bootstrap mode, the first 512 words of program ram are read-disabled but write-accessible. the contents of the bootstrap rom are listed in appendix a. note: the dsp56004 contains no program rom, but it has 512 words of program ram. the dsp56004rom contain a program rom, but it has only 256 words of program ram. the bootstrap code for each version is written appropriately for each type chip. 1.3.3.5 external memory the dsp56004 does not extend internal memory off chip. however, external memory can be added using the emi. see section 4 , external memory interface for a detailed description of the emi. 1.3.3.6 reserved memory spaces the memory spaces marked as reserved should not be accessed by the user. they are reserved for the expansion of future versions or variants of this dsp. write operations to the reserved range are ignored. read operations from addresses in the reserved range (with values greater than or equal to $2c00 in x memory space and $2700 in y memory space, and values from the reserved area of program memory space), return the value $000005, which is the opcode for the illegal instruction. if a read access is performed from the reserved area below address $2000 in x or y data memory, the resulting data will be undetermined. if an instruction fetch is attempted from addresses in the reserved area, the value returned is $000005, which is the opcode for the illegal instruction, causing an illegal instruction interrupt service. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview dsp56004 architectural overview motorola dsp56004 user? manual 1-16 1.3.4 input/output a variety of system configurations are facilitated by the dsp56004 input/output (i/o) structure. each i/o interface has its own control, status, and double-buffered data registers that are memory-mapped in the x data memory space (see table 1-3 ). table 1-3 on-chip peripheral memory map address register x:$ffff interrupt priority register (ipr) x:$fffe reserved x:$fffd pll control register (pctl) x:$fffc reserved x:$fffb reserved x:$fffa reserved x:$fff9 reserved x:$fff8 reserved x:$fff7 gpio control/data register (gpior) x:$fff6 emi write offset register (ewor) x:$fff5 reserved x:$fff4 reserved x:$fff3 shi receive fifo/transmit register (hrx/htx) x:$fff2 shi i 2 c slave address register (hsar) x:$fff1 shi host control/status register (hcsr) x:$fff0 shi host clock control register (hckr) x:$ffef emi refresh control register (ercr) x:$ffee emi data register 1 (edrr1/edwr1) x:$ffed emi offset register 1 (eor1) x:$ffec emi base address register 1 (ebar1) x:$ffeb emi control/status register (ecsr) x:$ffea emi data register 0 (edrr0/edwr0) x:$ffe9 emi offset register 0 (eor0) x:$ffe8 emi base address register 0 (ebar0) x:$ffe7 sai tx2 data register (tx2) x:$ffe6 sai tx1 data register (tx1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-17 dsp56004 user? manual motorola overview dsp56004 architectural overview the emi, shi, and sai also have several dedicated interrupt vector addresses and control bits to enable and disable interrupts (see table 1-2 on page 1-13). these interrupt vectors minimize the overhead associated with servicing an interrupt by immediately executing the appropriate service routine. each interrupt can be programmed to one of three maskable priority levels. 1.3.4.1 external memory interface the external memory interface (emi) is an i/o interface that enables the dsp to access external dynamic and/or static memory with little or no additional logic. the emi is implemented as a buffered peripheral rather than a transparent extension to internal memory. this interface facilitates the storage of audio samples for digital reverberation algorithms and permits simple implementation of large data delay buffers in external memory. the emi on the dsp56004 is designed to connect directly to dynamic ram (dram) of the following sizes: one or two 256 k 4?it chips one or two 1 m 4?it chips one or two 4 m 4?it chips when using static ram (sram), the emi may directly access up to 256 k 8 bits. the external data bus width may be 4 or 8 bits. data words of 8, 12, 16, 20 or 24 bits may be stored and retrieved via the emi with automatic packing and unpacking. in addition, the emi may be selected to operate in the sram/eprom absolute addressing mode. this allows connection to external memory devices for program bootstrap and data storage, as well as general parallel access to peripheral devices. x:$ffe5 sai tx0 data register (tx0) x:$ffe4 sai tx control/status register (tcs) x:$ffe3 sai rx1 data register (rx1) x:$ffe2 sai rx0 data register (rx0) x:$ffe1 sai rx control/status register (rcs) x:$ffe0 sai baud rate control register (brc) x:$ffdf reserved :: x:$ffc0 reserved table 1-3 on-chip peripheral memory map (continued) address register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . overview dsp56004 architectural overview motorola dsp56004 user? manual 1-18 1.3.4.2 serial host interface (shi) the serial host interface (shi) provides a serial path for communication and program/coefficient data transfers between the dsp and an external host processor or other serial peripheral devices. this interface can connect directly to one of two well-known and widely-used synchronous serial buses: the serial peripheral interface (spi) bus defined by motorola and the inter integrated-circuit control (i 2 c) bus defined by philips. the shi handles both spi and i 2 c bus protocols as required from a slave or a single-master device. in order to minimize dsp overhead, the shi supports single-, double-, and triple-byte data transfers. an optimal ten-word receive fifo register reduces the dsp overhead for data reception. 1.3.4.3 serial audio interface (sai) the dsp can communicate with other devices through the sai. the sai provides a synchronous full-duplex serial port for serial connection with a variety of audio devices, such as analog-to-digital (a/d) converters, digital-to-analog (d/a) converters, compact disk (cd) devices, etc. the sai implements a wide range of serial data formats in use by audio manufacturers. examples are: ? 2 s format (philips) cdp format (sony) mec format (matsushita) most industry-standard serial a/d and d/a formats the sai consists of independent transmit and receive sections and a common baud rate generator. the transmitter consists of three transmitters controlled by one transmitter controller. this enables simultaneous data transmission to as many as three stereo audio devices, or transmission of three separate stereo pairs of audio channels. the receiver consists of two receivers and a single receive controller. this enables simultaneous data reception from up to two stereo audio devices. the transmit and receive sections are fully asynchronous and may transmit and receive at different rates. 1.3.4.4 general purpose input/output the general purpose input/output (gpio) signals are used for control and handshake functions between the dsp and external circuitry. the gpio port has four dedicated signals (gpio0?pio3) that are controlled through a memory-mapped register. associated with each gpio signal is a data bit, a control bit, and a data direction bit that configures the pin as an input or an output, open-collector or normal. see section 7 for detailed information about gpio operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-19 dsp56004 user? manual motorola overview dsp56004 architectural overview f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual 2-1 section 2 signal descriptions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-2 dsp56004 user? manual motorola signal descriptions 2.1 signal groupings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 clock and pll signals . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5 external memory interface (emi) . . . . . . . . . . . . . . 2-7 2.6 interrupt and mode control . . . . . . . . . . . . . . . . . 2-10 2.7 serial host interface (shi) . . . . . . . . . . . . . . . . . . . 2-14 2.8 serial audio interface (sai) . . . . . . . . . . . . . . . . . . . 2-18 2.9 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.10 on-chip emulation (oncetm) port . . . . . . . . . . . . . 2-22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions signal groupings motorola dsp56004 user? manual 2-3 2.1 signal groupings the dsp56004 input and output signals are organized into the nine functional groups, as shown in table 2-1 . the individual signals are illustrated in figure 2-1 . table 2-1 dsp56004 functional group signal allocations functional group number of signals detailed description power (v cc )9 table 2-2 ground (gnd) 13 table 2-3 phase lock loop (pll) 3 table 2-4 external memory interface (emi) 29 table 2-5 and table 2-6 interrupt and mode control 4 table 2-7 serial host interface (shi) 5 table 2-8 serial audio interface (sai) 9 table 2-9 and table 2-10 general purpose input/output (gpio) 4 table 2-11 on-chip emulation (once) port 4 table 2-12 total 80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-4 dsp56004 user? manual motorola signal descriptions signal groupings figure 2-1 dsp56004 signals ma0?a14 md0?d7 mwr ma17/mcs1 /mras ma16/mcs2 /mcas gnd q v ccq reset moda/irqa modb/irqb modc/nmi ss /ha2 miso/sda sck/scl gnd s v ccs wsr sckr sdi0 dsck/os1 dsi/os0 dso dr once port c port b port a external memory mode/interrupt 80 signals serial host rec0 sdo1 tran1 wst sckt sdo0 tran0 interface mrd mcs0 serial audio interface interface mosi/ha0 sdo2 tran2 sdi1 rec1 gpio0?pio3 gpio hreq v ccp gnd p pcap pll pinit ma15/mcs3 extal gnd a v cca gnd d v ccd reset aa0249g port power inputs ground control 2 2 3 3 4 2 3 8 4 15 dsp56004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions power motorola dsp56004 user? manual 2-5 2.2 power 2.3 ground table 2-2 power inputs power name description v ccp pll power ? ccp provides isolated power for the phase lock loop (pll). the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. v ccq quiet power v ccq provides isolated power for the internal processing logic. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v cca address bus power ? cca provides isolated power for sections of the address bus i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v ccd data bus power ? ccd provides isolated power for sections of the data bus i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v ccs serial interface power ? ccs provides isolated power for the shi and sai. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. table 2-3 grounds ground name description gnd p pll ground ?nd p is ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.47 m f capacitor located as close as possible to the chip package. gnd q quiet ground ?nd q provides isolated ground for the internal processing logic. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd a address bus ground ?nd a provides isolated ground for sections of the address bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-6 dsp56004 user? manual motorola signal descriptions clock and pll signals 2.4 clock and pll signals note: while the pll on this dsp is identical to the pll described in the dsp56000 family manual , two of the signals have not been implemented externally. specifically, there is no plock signal or ckout signal available. therefore, the internal clock is not directly accessible and there is no external indication that the pll is locked. these signals were omitted to reduce the number of pins and allow this dsp to be put in a smaller, less expensive package. gnd d data bus ground ?nd d provides isolated ground for sections of the data bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd s serial interface ground ?nd s provides isolated ground for the shi and sai. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. table 2-4 clock and pll signals signal name signal type state during reset signal description extal input input external clock/crystal ?his input should be connected to an external clock source. if the pll is enabled, this signal is internally connected to the on-chip pll. the pll can multiply the frequency on the extal pin to generate the internal dsp clock. the pll output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two pll output clock periods. if the pll is disabled, extal is divided by two to produce the four-phase instruction cycle clock. table 2-3 grounds (continued) ground name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions external memory interface (emi) motorola dsp56004 user? manual 2-7 2.5 external memory interface (emi) pcap input input pll filter capacitor ?his input is used to connect a high-quality (high ??factor) external capacitor needed for the pll filter. the capacitor should be as close as possible to the dsp with heavy, short traces connecting one terminal of the capacitor to pcap and the other terminal to v ccp . the required capacitor value is specified in the dsp56004 technical data sheets. when short lock time is critical, low dielectric absorption capacitors such as polystyrene, polypropylene, or teflon are recommended. if the pll is not used (i.e., it remains disabled at all times), there is no need to connect a capacitor to the pcap pin. it may remain unconnected, or be tied to either v cc or gnd. pinit input input pll initialization (pinit) ?uring the assertion of hardware reset, the value on the pinit line is written into the pen bit of the pctl register. when set, the pen bit enables the pll by causing it to derive the internal clocks from the pll voltage controlled oscillator output. when the bit is cleared, the pll is disabled and the dsp? internal clocks are derived from the clock connected to the extal signal. after hardware reset is deasserted, the pinit signal is ignored. table 2-5 external memory interface (emi) signals signal name signal type state during reset signal description ma0?a14 output table 2-6 memory address lines 0?4 ?a0?a10 provide the multiplexed row/column addresses for dram accesses and ma0?a14 provide the non-multiplexed address lines 0?4 for sram accesses. table 2-4 clock and pll signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-8 dsp56004 user? manual motorola signal descriptions external memory interface (emi) ma15/mcs3 output table 2-6 memory address line 15 (ma15)/memory chip select 3 (mcs3 ) ?his line functions as the non-multiplexed address line 15 or as memory chip select 3 for sram accesses. ma16/mcs2 / mcas output table 2-6 memory address line 16 (ma16)/memory chip select 2 (mcs2 )/memory column address strobe (mcas ) ?this line functions as the non-multiplexed address line 16 or as memory chip select 2 for sram accesses. this line also functions as the memory column address strobe (mcas ) during dram accesses. ma17/mcs1 / mras output table 2-6 memory address line 17 (ma17)/memory chip select 1 (mcs1 )/memory row address strobe (mras ) ?his line functions as the non-multiplexed address line 17 or as chip select 1 for sram accesses. this line also functions as the memory row address strobe during dram accesses. mcs0 output table 2-6 memory chip select 0 ?his line functions as memory chip select 0 for sram accesses. mwr output table 2-6 memory write strobe ?his line is asserted when writing to external memory. mrd output table 2-6 memory read strobe ?his line is asserted when reading external memory. md0?d7 bi- directional tri-stated data bus ?hese signals provide the bidirectional data bus for emi accesses. they are inputs during reads from external memory, outputs during writes to external memory, and tri-stated if no external access is taking place. if the data bus width is defined as four bits wide, only signals md0?d3 are active, while signals md4?d7 remain tri-stated. while tri-stated, md0?d7 are disconnected from the pins and do not require external pull-ups. table 2-5 external memory interface (emi) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions external memory interface (emi) motorola dsp56004 user? manual 2-9 . table 2-6 emi operating states signal function operating mode hardware reset software reset individual reset stop mode ma0?a14 driven high previous state previous state previous state ma15/mcs3 ma15 mcs3 driven high driven high driven high driven high previous state driven high previous state driven high ma16/mcs2 / mcas ma16 mcs2 mcas: dram refresh disabled dram refresh enabled driven high driven high driven high driven high driven high driven high driven high driven high previous state driven high driven high driven low previous state driven high driven high driven high ma17/mcs1 / mras ma17 mcs1 mras: dram refresh disabled dram refresh enabled driven high driven high driven high driven high driven high driven high driven high driven high previous state driven high driven high driven low previous state driven high driven high driven high mcs0 driven high driven high driven high driven high mwr driven high driven high driven high driven high mrd driven high driven high driven high driven high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-10 dsp56004 user? manual motorola signal descriptions interrupt and mode control 2.6 interrupt and mode control the interrupt and mode control signals select the dsp? operating mode as it comes out of hardware reset and receives interrupt requests from external sources after reset. table 2-7 interrupt and mode control signals signal name signal type state during reset signal description moda irqa input input (moda) mode select a ?his input signal has three functions: to work with the modb and modc signals to select the dsp? initial operating mode, to allow an external device to request a dsp interrupt after internal synchronization, and to turn on the internal clock generator when the dsp in the stop processing state, causing the dsp to resume processing. moda is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the moda signal changes to the external interrupt request irqa . the dsp operating mode can be changed by software after reset. external interrupt request a (irqa ) ?he irqa input is a synchronized external interrupt request. it may be programmed to be level-sensitive or negative-edge-triggered. when the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqa will generate multiple interrupts also increases. while the dsp is in the stop mode, asserting irqa gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. hardware reset causes this input to function as moda. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions interrupt and mode control motorola dsp56004 user? manual 2-11 modb irqb input input (modb) mode select b ?this input signal has two functions: to work with the moda and modc signals to select the dsp? initial operating mode, and to allow an external device to request a dsp interrupt after internal synchronization. modb is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the modb signal changes to the external interrupt request irqb . the dsp operating mode can be changed by software after reset. external interrupt request b (irqb )?he irqb input is a synchronized external interrupt request. it may be programmed to be level-sensitive or negative-edge-triggered. when the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqb will generate multiple interrupts also increases. hardware reset causes this input to function as modb. table 2-7 interrupt and mode control signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-12 dsp56004 user? manual motorola signal descriptions interrupt and mode control modc/ nmi input, edge- triggered input (modc) mode select c ?his input signal has two functions: to work with the moda and modb signals to select the dsp? initial operating mode, and to allow an external device to request a dsp interrupt after internal synchronization. modc is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the modc signal changes to the non-maskable interrupt request, nmi . the dsp operating mode can be changed by software after reset. non-maskable interrupt request ?he nmi input is a negative-edge-triggered external interrupt request. this is a level 3 interrupt that can not be masked out. triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on nmi will generate multiple interrupts also increases. hardware reset causes this input to function as modc. table 2-7 interrupt and mode control signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions interrupt and mode control motorola dsp56004 user? manual 2-13 reset input active reset this input causes a direct hardware reset of the processor. when reset is asserted, the dsp is initialized and placed in the reset state. a schmitt-trigger input is used for noise immunity. when the reset signal is deasserted, the initial dsp operating mode is latched from the moda, modb, and modc signals. the dsp also samples the pinit signal and writes its status into the pen bit of the pll control register. when the dsp comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the reset signal. however, the probability that noise on reset will generate multiple resets increases with increasing rise time of the reset signal. for proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware reset state. table 2-7 interrupt and mode control signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-14 dsp56004 user? manual motorola signal descriptions serial host interface (shi) 2.7 serial host interface (shi) the serial host interface (shi) has five i/o signals, which may be configured to operate in either spi or i 2 c mode. table 2-8 lists the shi signals. table 2-8 serial host interface (shi) signals signal name signal type state during reset signal description sck scl input or output input or output tri-stated spi serial clock (sck) ?he sck signal is an output when the spi is configured as a master, and a schmitt-trigger input when the spi is configured as a slave. when the spi is configured as a master, the sck signal is derived from the internal shi clock generator. when the spi is configured as a slave, the sck signal is an input, and the clock signal from the external master synchronizes the data transfer. the sck signal is ignored by the spi if it is defined as a slave and the slave select (ss ) signal is not asserted. in both the master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi transfer protocol. i 2 c serial clock (scl) scl carries the clock for bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. scl should be connected to v cc through a pull-up resistor. the maximum allowed internally generated bit clock frequency is f osc / 4 for the spi mode and f osc / 6 for the i 2 c mode where f osc is the clock on extal. the maximum allowed externally generated bit clock frequency is f osc / 3 for the spi mode and f osc / 5 for the i 2 c mode. this signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions serial host interface (shi) motorola dsp56004 user? manual 2-15 miso sda input or output input or output tri-stated spi master-in-slave-out (miso) ?when the spi is configured as a master, miso is the master data input line. the miso signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when configured for the spi slave mode, and tri-stated if configured for the spi slave mode when ss is deasserted. i 2 c serial data and acknowledge (sda) ?n i 2 c mode, sda is a schmitt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v cc through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is high in the case of start and stop events. a high-to-low transition of the sda line while scl is high is an unique situation, and is defined as the start event. a low-to-high transition of sda while scl is high is an unique situation, and is defined as the stop event. note: this line is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). table 2-8 serial host interface (shi) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-16 dsp56004 user? manual motorola signal descriptions serial host interface (shi) mosi ha0 input or output input tri-stated spi master-out-slave-in (miso) ?hen the spi is configured as a master, mosi is the master data output line. the mosi signal is used in conjunction with the miso signal for transmitting and receiving serial data. mosi is the slave data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode. i 2 c slave address 0 (ha0) this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when the shi is configured for the i 2 c master mode. note: this signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). ss ha2 input input tri-stated spi slave select (ss ) ?his signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for transfer. when configured for the spi master mode, this signal should be kept deasserted. if it is asserted while configured as spi master, a bus error condition will be flagged. i 2 c slave address 2 (ha2) ?his signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. if ss is deasserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. note: this signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). table 2-8 serial host interface (shi) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions serial host interface (shi) motorola dsp56004 user? manual 2-17 hreq input or output tri-stated host request ?his signal is an active low schmitt-trigger input when configured for the master mode, but an active low output when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input and when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing the data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. note: this signal is tri-stated during hardware, software, individual reset, or when the hreq[1:0] bits (in the hcsr) are cleared (no need for external pull-up in this state). table 2-8 serial host interface (shi) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-18 dsp56004 user? manual motorola signal descriptions serial audio interface (sai) 2.8 serial audio interface (sai) the sai is composed of separate receiver and transmitter sections. 2.8.1 sai receiver section table 2-9 serial audio interface (sai) receiver signals signal name signal type state during reset signal description sdi0 input tri-stated serial data input 0 ?hile in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. sdi0 is the serial data input for receiver 0. note: this signal is high impedance during hardware or software reset, while receiver 0 is disabled (r0en = 0), or while the dsp is in the stop state. sdi1 input tri-stated serial data input 1 ?hile in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. sdi1 is the serial data input for receiver 1. note: this signal is high impedance during hardware or software reset, while receiver 1 is disabled (r1en = 0), or while the dsp is in the stop state. sckr input or output tri-stated receive serial clock ?ckr is an output if the receiver section is programmed as a master, and a schmitt-trigger input if programmed as a slave. while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. note: sckr is high impedance if all receivers are disabled (individual reset) and during hardware or software reset, or while the dsp is in the stop state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions serial audio interface (sai) motorola dsp56004 user? manual 2-19 wsr input or output tri-stated word select receive (wsr) ?sr is an output if the receiver section is configured as a master, and a schmitt-trigger input if configured as a slave. wsr is used to synchronize the data word and to select the left/right portion of the data sample. note: wsr is high impedance if all receivers are disabled (individual reset), during hardware reset, during software reset, or while the dsp is in the stop state. while in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary. table 2-9 serial audio interface (sai) receiver signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-20 dsp56004 user? manual motorola signal descriptions serial audio interface (sai) 2.8.2 sai transmitter section table 2-10 serial audio interface (sai) transmitter signals signal name signal type state during reset signal description sdo0 output driven high serial data output 0 (sdo0) ?do0 is the serial output for transmitter 0. sdo0 is driven high if transmitter 0 is disabled, during individual reset, hardware reset, and software reset, or when the dsp is in the stop state. sdo1 output driven high serial data output 1 (sdo1) ?do1 is the serial output for transmitter 1. sdo1 is driven high if transmitter 1 is disabled, during individual reset, hardware reset and software reset, or when the dsp is in the stop state. sdo2 output driven high serial data output 2 (sdo2) ?do2 is the serial output for transmitter 2. sdo2 is driven high if transmitter 2 is disabled, during individual reset, hardware reset and software reset, or when the dsp is in the stop state. sckt input or output tri-stated serial clock transmit (sckt) ?his signal provides the clock for the sai. sckt can be an output if the transmit section is configured as a master, or a schmitt-trigger input if the transmit section is configured as a slave. when the sckt is an output, it provides an internally generated sai transmit clock to external circuitry. when the sckt is an input, it allows external circuitry to clock data out of the sai. note: sckt is high impedance if all transmitters are disabled (individual reset), during hardware reset, software reset, or while the dsp is in the stop state. while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions general purpose i/o motorola dsp56004 user? manual 2-21 2.9 general purpose i/o wst input or output tri-stated word select transmit (wst) ?st is an output if the transmit section is programmed as a master, and a schmitt-trigger input if it is programmed as a slave. wst is used to synchronize the data word and select the left/right portion of the data sample. note: wst is high impedance if all transmitters are disabled (individual reset), during hardware or software reset, or while the dsp is in the stop state. while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. table 2-11 general purpose i/o (gpio) signals signal name signal type state during reset signal description gpio0? gpio3 standard output, open-drain output, or input disconnected gpio lines can be used for control and handshake functions between the dsp and external circuitry. each gpio line can be configured individually as disconnected, open-drain output, standard output, or an input. note: hardware reset or software reset configures all the gpio lines as disconnected (external circuitry connected to these pins may need pull-ups until the pins are configured for operation). table 2-10 serial audio interface (sai) transmitter signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-22 dsp56004 user? manual motorola signal descriptions on-chip emulation (once tm ) port 2.10 on-chip emulation (once tm ) port there are four signals associated with the once port controller and its serial interface. table 2-12 on-chip emulation port signals signal name signal type state during reset signal description dsi os0 input output output, driven low debug serial input (dsi) ?he dsi signal is the signal through which serial data or commands are provided to the once port controller. the data received on the dsi signal will be recognized only when the dsp has entered the debug mode of operation. data must have valid ttl logic levels before the serial clock falling edge. data is al ways shifted into the once port most significant bit (msb) first. operating status 0 (os0) when the dsp is not in the debug mode, the os0 signal provides information about the dsp status if it is an output and used in conjunction with the os1 signal. when switching from output to input, the signal is tri-stated. note: if the once port is in use, an external pull-down resistor should be attached to the dsi/os0 signal. if the once port is not in use, the resistor is not required. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions on-chip emulation (once tm ) port motorola dsp56004 user? manual 2-23 dsck os1 input output output, driven low debug serial clock (dsck) ?he dsck/os1 signal, when an input, is the signal through which the serial clock is supplied to the once port. the serial clock provides pulses required to shift data into and out of the once port. data is clocked into the once port on the falling edge and is clocked out of the once port on the rising edge. operating status 1 (os1) ?f the os1 signal is an output and used in conjunction with the os0 signal, it provides information about the dsp status when the dsp is not in the debug mode. the debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. the signal is tri-stated when it is changing from input to output. note: if the once port is in use, an external pull-down resistor should be attached to the dsck/os1 pin. if the once port is not in use, the resistor is not required. table 2-12 on-chip emulation port signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-24 dsp56004 user? manual motorola signal descriptions on-chip emulation (once tm ) port dso output driven high debug serial output (dso) ?he dso line provides the data contained in one of the once port controller registers as specified by the last command received from the command controller. the most significant bit (msb) of the data word is always shifted out of the once port first. data is clocked out of the once port on the rising edge of dsck. the dso line also provides acknowledge pulses to the external command controller. when the dsp enters the debug mode, the dso line will be pulsed low to indicate that the once port is waiting for commands. after receiving a read command, the dso line will be pulsed low to indicate that the requested data is available and the once port is ready to receive clock pulses in order to deliver the data. after receiving a write command, the dso line will be pulsed low to indicate that the once port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. note: during hardware reset and when idle, the dso line is held high. table 2-12 on-chip emulation port signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions on-chip emulation (once tm ) port motorola dsp56004 user? manual 2-25 dr input input debug request (dr ) ?he debug request input provides a means of entering the debug mode of operation. this signal, when asserted (pulled low), will cause the dsp to finish the current instruction being executed, to save the instruction pipeline information, to enter the debug mode, and to wait for commands to be entered from the debug serial input line. while the dsp is in the debug mode, the user can reset the once port controller by asserting dr , waiting for an acknowledge pulse on dso, and then deasserting dr . it may be necessary to reset the once port controller in cases where synchronization between the once port controller and external circuitry is lost. asserting dr when the dsp is in the wait or the stop mode, and keeping it asserted until an acknowledge pulse in the dsp is produced, puts the dsp into the debug mode. after receiving the acknowledge pulse, dr must be deasserted before sending the first once port command. for more information, see methods of entering the debug mode in the dsp56000 family manual . note: if the once port is not in use, an external pull-up resistor should be attached to the dr line. table 2-12 on-chip emulation port signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-26 dsp56004 user? manual motorola signal descriptions on-chip emulation (once tm ) port f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section 3 memory, operating modes, and interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-2 dsp56004 user? manual motorola memory, operating modes, and interrupts 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 dsp56004 program and data memory . . . . . . . . . . . 3-3 3.3 operating mode register (omr). . . . . . . . . . . . . . . . 3-9 3.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.5 interrupt priority register. . . . . . . . . . . . . . . . . . 3-11 3.6 phase lock loop (pll) configuration . . . . . . . . . 3-15 3.7 hardware reset operation. . . . . . . . . . . . . . . . . . . 3-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory, operating modes, and interrupts introduction motorola dsp56004 user? manual 3-3 3.1 introduction the dsp56004 program and data memories are independent, and the on-chip data memory is divided into two separate memory spaces, x and y. there are also two on-chip data roms in the x and y data memory spaces, and a bootstrap rom. the data memories are divided into two independent spaces to work with the two address alus to feed two operands simultaneously to the data alu. this section also includes details of the interrupt vectors and priorities and describes the effect of a hardware reset on the pll multiplication factor (mf). 3.2 dsp56004 program and data memory external memory cannot be accessed as a direct extension of the internal memory. the standard dsp56004 contains no on-chip program rom. the dsp56004rom can have a generic rom code (listed in appendix a ), or other programming supplied by the application developer. table 3-1 shows the available internal memory, depending on the specific dsp56004 configuration. note: location x:$fffe is the bus control register (bcr) for the dsp56000 core processor. although labelled reserved on this dsp, the bcr remains active. the bcr is cleared by reset and should remain cleared (i.e., do not write to this location) even though this dsp does not require the bcr function. the internal program and data memory maps for the non-rom dsp56004 are shown in figure 3-1 on page 3-4. the internal program and data memory maps for the dsp56004rom are shown in figure 3-2 on page 3-4. table 3-1 memory configurations (word width is 24 bits) part type mode program x data y data boot- strap rom rom ram rom ram rom ram dsp56004 none 512 256 log 2 x 2 x 256 256 sine 256 64 dsp56004rom 2560* 256 256* 256 256* 256 32 *these roms may be factory-programmed with data/program provided by the application developer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-4 dsp56004 user? manual motorola memory, operating modes, and interrupts dsp56004 program and data memory program memory p: ram = 512 24 p: rom = 0 24 x data memory x: ram = 256 24 x: rom = 256 24 y data memory y: ram = 256 24 y: rom = 256 24 $ffff reserved on-chip peripherals reserved $ffc0 $ffbf reserved $0200 $01ff internal ram internal rom internal rom $0100 $00ff internal ram internal ram $0000 figure 3-1 dsp56004 internal memory map program memory p: ram = 256 24 p: rom = 2560 24 x data memory x: ram = 256 24 x: rom = 256 24 y data memory y: ram = 256 24 y: rom = 256 24 $ffff reserved on-chip peripherals reserved $ffc0 $ffbf reserved $0e00 $0dff internal rom $0400 $03ff reserved $0200 $01ff internal rom internal rom $0100 $00ff internal ram internal ram internal ram $0000 figure 3-2 dsp56004rom internal memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory, operating modes, and interrupts dsp56004 program and data memory motorola dsp56004 user? manual 3-5 3.2.1 x data rom the x data rom occupies locations 256?11 in the x data memory space. the x data rom is factory programmed with a log 2 x table (for 0.5 x < 1) in locations 256?83 and a 2 x table (for 0.5 2 x < 1) in locations 384?11. the contents of the x data rom are shown in appendix a . for more detailed information, contact the motorola dsp technical help line. 3.2.1.1 assembler routine to access the log 2 (x) table the routine log 2 _addr receives a normalized value of x in register x0 and returns the address in r0 that points to the log 2 (x) value. ; x = 0.5 (1 + (addr - 256/128)) ; where addr ranges from ; 256 to 383 addr = 128 + 256 * x log2_addr move #>$80,a mac x0,#15,a move a1,r0 rts 3.2.1.2 assembler routine to access the 2 x table the routine pow2_addr receives a normalized value of x in y0 and returns the address in r1 that points to the 2 x value. ; x= -1.0 (1 - (addr - 384/128)); where addr ranges from ; 384 to 511 addr = 128 * x + 512 pow2_addr move #>$200,a mac y0,#16,a move a1,r1 rts 3.2.2 y data rom the y data rom occupies locations 256?11 in the y data memory space. the y data rom is factory programmed with a full, four-quadrant sine wave table. the contents of the y data rom are listed in appendix a . for more detailed information, contact the motorola dsp technical help line. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-6 dsp56004 user? manual motorola memory, operating modes, and interrupts dsp56004 program and data memory 3.2.3 dsp56004 bootstrap rom the dsp56004 incorporates 64 words of bootstrap rom. the bootstrap rom is accessible when mc:mb:ma are not equal to 000. the dsp56004 can bootstrap from external eprom attached to the emi, through the serial host interface (shi) using the spi protocol, or through the shi using the i 2 c protocol, depending on how the three mode pins (mc:mb:ma) are configured. programs can be loaded from external eprom if mc:mb:ma = 001. the internal program ram is loaded with 1,536 consecutive bytes from an eprom connected to the emi. the eprom is located at the emi address $0, when operating the emi in the sram absolute addressing mode (eam2-eam0 = 000). it is assumed that the eprom is selected (enabled) through the gpio3 pin, which is driven low in this bootstrap mode. the gpio3 output is programmed to be of the active high/active low type. the bytes will be packed into 512 24-bit words and stored in contiguous program ram memory locations starting at p:$0000. note: the routine loads data starting with the least significant byte of p:$0000. the once port is enabled by the emi bootstrap. programs can be loaded from the serial host interface (shi) in the spi mode if mc:mb:ma = 101, or in the i 2 c mode if mc:mb:ma = 111. the internal program ram is loaded with up to 512 words that are 24-bits long and are received through the shi. the shi operates in the slave mode, with the 10-word fifo enabled, and with the hreq pin enabled for receive operation. the once port is enabled by the bootstrap code. the contents of the bootstrap rom are listed appendix a . 3.2.4 dsp56004rom bootstrap rom the dsp56004rom incorporates 32 words of bootstrap rom. the bootstrap rom is accessible when mc:mb:ma are not equal to 000. the bootstrap code is used to implement the operating modes upon hardware reset. the prom module is always enabled and is accessible via the once port whenever debug mode is used. note: the dsp56004rom version has 256 words of program ram and the boostrap program in this version has been adapted to this program ram size. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory, operating modes, and interrupts dsp56004 program and data memory motorola dsp56004 user? manual 3-7 3.2.5 dsp56004rom program rom for the dsp56004rom only, the program rom occupies locations $2000?47ff in the program memory space. the functions contained in the program rom are listed in appendix a . for more detailed information, contact the motorola dsp technical help line. note: the standard dsp56004 contains no program rom. 3.2.6 reserved memory spaces the reserved memory spaces should not be accessed by the user. they are reserved for future expansion. write operations to the reserved range are ignored. read operations from addresses in the reserved range return the value $000005. if an instruction fetch is attempted from an address in the reserved area, the value returned is $000005, which is the opcode for the illegal instruction. 3.2.7 internal i/o memory map the dsp56004 on-chip peripheral modules have their register files programmed to the addresses in the internal i/o memory range, as shown in table 3-2 on page 3-7. note: location x:$fffe is the bus control register (bcr) for the dsp56000 core. although labelled reserved on the dsp56004, the bcr remains active. the bcr is cleared by reset and should remain cleared (i.e., do not write to this location) since the dsp56004 does not make use of the bcr function. table 3-2 internal i/o memory map location register x: $ffff interrupt priority register (ipr) x: $fffe reserved x: $fffd pll control register (pctl) x: $fffc reserved x: $fffb reserved x: $fffa reserved x: $fff9 reserved x: $fff8 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-8 dsp56004 user? manual motorola memory, operating modes, and interrupts dsp56004 program and data memory x: $fff7 gpio control/data register (gpior) x: $fff6 emi write offset register (ewor) x: $fff5 reserved x: $fff4 reserved x: $fff3 shi receive fifo/transmit register (hrx/htx) x: $fff2 shi i 2 c slave address register (hsar) x: $fff1 shi host control/status register (hcsr) x: $fff0 shi host clock control register (hckr) x: $ffef emi refresh control register (ercr) x: $ffee emi data register 1 (edrr1/edwr1) x: $ffed emi offset register 1 (eor1) x: $ffec emi base address register 1 (ebar1) x: $ffeb emi control/status register (ecsr) x: $ffea emi data register 0 (edrr0/edwr0) x: $ffe9 emi offset register 0 (eor0) x: $ffe8 emi base address register 0 (ebar0) x: $ffe7 sai tx2 data register (tx2) x: $ffe6 sai tx1 data register (tx1) x: $ffe5 sai tx0 data register (tx0) x: $ffe4 sai tx control/status register (tcs) x: $ffe3 sai rx1 data register (rx1) x: $ffe2 sai rx0 data register (rx0) x: $ffe1 sai rx control/status register (rcs) x: $ffe0 sai baud rate control register (brc) x: $ffdf reserved :: x: $ffc0 reserved table 3-2 internal i/o memory map (continued) location register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory, operating modes, and interrupts operating mode register (omr) motorola dsp56004 user? manual 3-9 3.3 operating mode register (omr) the operating mode register (omr) is illustrated in figure 3-3 . 3.3.1 dsp operating mode (mc, mb, ma)?its 4, 1, and 0 the dsp operating mode bits, mc, mb, and ma, select the operating mode of the dsp56004. these operating modes are described in section 3.4 operating modes on the following page. on hardware reset, mc, mb, and ma are loaded from the external mode select pins modc, modb, and moda, respectively. after the dsp leaves the reset state, mc, mb, and ma can be changed under software control. 3.3.2 stop delay (sd)?it 6 when leaving the stop state, the stop delay (sd) bit is interrogated. if cleared (sd = 0), a 65,535 core clock cycle delay (131,072 t states) is implemented before continuation of the stop instruction cycle. if the sd bit is set (sd = 1), the delay before continuation of the stop instruction cycle is set as eight clock cycles (16 t states). when the dsp is driven by a stable external clock source, setting the sd bit before executing the stop instruction will allow a faster start up of the dsp. figure 3-3 operating mode register (omr) bits 2,3, 5 ,and 7?3 are reserved, read as 0s, and should be written with 0s ma mb mc sd 0 1 2 3 4 5 6 23 7 operating mode a,b operating mode c stop delay aa0291k for future compatibility. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-10 dsp56004 user? manual motorola memory, operating modes, and interrupts operating modes 3.4 operating modes the dsp56004 operating modes are described in detail below and summarized in table 3-3 on page 3-11. the operating modes for the dsp56004 are identical to the dsp56004rom except that there is no mode 2, and if mode 0 is selected during hardware reset, the chip will default to mode 1 instead of mode 2. each operating mode is described below. mode 0 ?n this mode, the internal program ram is enabled and the bootstrap rom is disabled. all bootstrap programs end by selecting this operating mode. this is identical to the dsp56001/dsp56002 mode 0. it is not possible to reach this operating mode during hardware reset. if an attempt is made, the chip will default to mode 1. mode 1 bootstrap terminates by setting the operating mode to 0 and jumping to the reset vector at address $0000. mode 1 ?n this mode, the bootstrap rom is enabled and the bootstrap program is executed after hardware reset. the internal program ram is loaded with up to 512 words from an external byte-wide static memory connected to the external memory interface (emi). the emi operates in the sram absolute addressing mode with the slowest sram timing. it is assumed that the chip select control for the external memory is the gpio3 pin. the on-chip x and y data memories are cleared. this bootstrap mode enables operation of the once interface immediately after clearing the internal memories and before starting to load from the external memory; this permits using the once port to stop the bootstrap program and load the internal program ram through the once port. mode 1 bootstrap terminates by setting the operating mode to mode 0 and jumping to the reset vector at address $0000. mode 2 ?or the dsp56004rom, in this mode, the bootstrap rom is enabled and the bootstrap program is executed after hardware reset. the bootstrap program ends up in the first location of the program rom (program address $2000). for the dsp56004, this mode is reserved. mode 3 ?eserved mode 4 ?eserved mode 5 ?n this mode, the bootstrap rom is enabled and the bootstrap program is executed after hardware reset. the internal program ram is loaded with up to 512 words from the serial host interface (shi). the shi operates in the spi slave mode, with 24-bit word width. the on-chip x and y data memories are cleared. this bootstrap mode enables operation of the once interface immediately after clearing the internal memories and before f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory, operating modes, and interrupts interrupt priority register motorola dsp56004 user? manual 3-11 starting to load from the external memory; this permits using the once port to stop the bootstrap program and load the internal program ram through the once port. mode 5 bootstrap terminates by setting the operating mode to mode 0 and jumping to the reset vector at address $0000. mode 6 ?eserved mode 7 ?n this mode, the bootstrap rom is enabled and the bootstrap program is executed after hardware reset. the internal program ram is loaded with up to 512 words from the serial host interface (shi). the shi operates in the i 2 c slave mode, with 24-bit word width. the on-chip x and y data memories are cleared. this bootstrap mode enables operation of the once interface immediately after clearing the internal memories and before starting to load from the external memory; this permits using the once port to stop the bootstrap program and load the internal program ram through the once port. mode 7 bootstrap terminates by setting the operating mode to mode 0 and jumping to the reset vector at address $0000. note: the once port operation is enabled at hardware reset. this means the device can enter the debug mode at any time after hardware reset. 3.5 interrupt priority register interrupt priorities are determined in the 24-bit interrupt priority register (ipr). the interrupt priority level (ipl) for each on-chip peripheral device and for two of the external interrupt sources, can be programmed, under software control, to one of three maskable priority levels (ipl 0,1, or 2). ipls are set by writing to the ipr. the ipr configuration is shown in figure 3-4 . table 3-3 operating modes mode mmm c b a operating mode 0 000 normal operation, bootstrap disabled 1 001 bootstrap from emi, once port enabled 2 010 wake up in program rom address $2000 (dsp56004rom) 3 011 reserved 4 100 reserved 5 101 bootstrap from shi (spi mode)i, once port enabled 6 110 reserved 7 111 bootstrap from shi (i 2 c mode)i, once port enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-12 dsp56004 user? manual motorola memory, operating modes, and interrupts interrupt priority register bits 0? of the ipr are used by the dsp56000 core for two of the external interrupt request inputs, irqa (ial[2:0]) and irqb (ibl[2:0]). assuming the same ipl, irqa has higher priority than irqb . bits 6? and 16?3 are reserved for future use. bits 10?5 are available for determining ipls for each peripheral (emi, shi, sai). two ipl bits are required for each peripheral interrupt group. the interrupt priorities are shown in table 3-4 and the interrupt vectors are shown in table 3-5 . figure 3-4 interrupt priority register (address x:$ffff) table 3-4 interrupt priorities priority interrupt level 3 (nonmaskable) highest lowest hardware reset illegal instruction nmi stack error trace swi ial1 ial0 ial2 ibl0 ibl1 ibl2 sal0 sal1 0 1110987654321 reserved, read as 0, and should be written with 0s for future compatibility. shl1 shl0 eml0 eml1 12 23 22 21 20 19 18 17 16 15 14 13 irqa mode irqb mode reserved sai ipl shi ipl emi ipl reserved aa0292 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory, operating modes, and interrupts interrupt priority register motorola dsp56004 user? manual 3-13 levels 0, 1, 2 (maskable) highest lowest irqa irqb sai receiver exception sai transmitter exception sai left channel receiver sai left channel transmitter sai right channel receiver sai right channel transmitter shi bus error shi receive overrun error shi transmit underrun error shi receive fifo full shi transmit data shi receive fifo not empty emi ebar0 memory wrap emi ebar1 memory wrap emi read data emi write data table 3-5 interrupt vectors address interrupt source p: $0000 hardware reset p: $0002 stack error p: $0004 trace p: $0006 swi p: $0008 irqa p: $000a irqb table 3-4 interrupt priorities (continued) priority interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-14 dsp56004 user? manual motorola memory, operating modes, and interrupts interrupt priority register p: $000c reserved p: $000e reserved p: $0010 sai left channel transmitter if txil = 0 p: $0012 sai right channel transmitter if txil = 0 p: $0014 sai transmitter exception if txil = 0 p: $0016 sai left channel receiver if rxil = 0 p: $0018 sai right channel receiver if rxil = 0 p: $001a sai receiver exception if rxil = 0 p: $001c reserved p: $001e nmi p: $0020 shi transmit data p: $0022 shi transmit underrun error p: $0024 shi receive fifo not empty p: $0026 reserved p: $0028 shi receive fifo full p: $002a shi receive overrun error p: $002c shi bus error p: $002e reserved p: $0030 emi write data p: $0032 emi read data p: $0034 emi ebar0 memory wrap p: $0036 emi ebar1 memory wrap p: $0038 reserved :: p: $003c reserved p: $003e illegal instruction p: $0040 sai left channel transmitter if txil = 1 p: $0042 sai right channel transmitter if txil = 1 p: $0044 sai transmitter exception if txil = 1 p: $0046 sai left channel receiver if rxil = 1 table 3-5 interrupt vectors (continued) address interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory, operating modes, and interrupts phase lock loop (pll) configuration motorola dsp56004 user? manual 3-15 3.6 phase lock loop (pll) configuration section 9 of the dsp56000 family manual provides detailed information about the phase lock loop (pll). the pll multiplication factor (mf) and the clock applied to extal determine the frequency at which the voltage controlled oscillator (vco) will oscillate, that is, the output frequency of the pll. if the pll is used as the dsp internal clock: the pll vco output is used directly as the internal dsp clock if the pll control register (pctl) chip clock source bit (csrc) is set, and the pll vco frequency is divided by the low power divider (lpd) and then used as the internal dsp clock if csrc is cleared. the dsp56004 pll multiplication factor is set to $500 during hardware reset, which means that the multiplication factor bits (mf[11:0]) in the pctl are set to $1f3. the pll may be disabled (pen = 0) upon reset by pulling the pinit pin low. the dsp will subsequently operate at the frequency of the clock applied to the extal pin until the pen bit is set. this reset value cannot be modified by the user until the dsp comes out of reset. the low power divider (lpd) division factor bits (df[3:0] in the pctl) are cleared during hardware reset. once the pen bit is set, it cannot be cleared by software. p: $0048 sai right channel receiver if rxil = 1 p: $004a sai receiver exception if rxil = 1 p: $004c reserved :: p: $007e reserved table 3-5 interrupt vectors (continued) address interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-16 dsp56004 user? manual motorola memory, operating modes, and interrupts hardware reset operation 3.7 hardware reset operation the processor enters the reset processing state after the external reset pin is asserted (hardware reset occurs) for the specified minimum time (see dsp56004 technical data sheet). the reset state: resets internal peripheral devices by initializing their control registers as described in the individual peripheral sections, sets the modifier registers to $ffff, clears the interrupt priority register (ipr), clears the stack pointer (sp), clears the scaling mode (s[1:0]), trace mode (t), loop flag (lf), double precision multiply mode (dm), and condition code register (ccr) bits in the status register (sr) and sets the interrupt mask (i[1:0]) bits, and clears the stop delay (sd) bit and the program ram enable (pea and peb) bits in the omr. the dsp remains in the reset state until the reset pin is deasserted. when the processor leaves the reset state it: loads the chip operating mode (mc, mb, and ma) bits of the omr from the external mode select pins (modc, modb, moda), and begins program execution of the bootstrap rom starting at address $0000. figure 3-5 pll configuration divider out extal vco out mf[11:0] df[3:0] phase detector (pd) charge pump loop filter voltage controlled oscillator (vco) low power divider 2 0 to 2 15 multiplication factor 1 to 4096 frequency multiplier aa0293k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual 4-1 section 4 external memory interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-2 dsp56004 user? manual motorola external memory interface 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 emi programming model . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3 emi address generation . . . . . . . . . . . . . . . . . . . . . . 4-23 4.4 dram refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.5 emi operating considerations. . . . . . . . . . . . . . . . 4-38 4.6 data-delay structure . . . . . . . . . . . . . . . . . . . . . . . . 4-46 4.7 emi-to-memory connection . . . . . . . . . . . . . . . . . . . 4-48 4.8 emi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface introduction motorola dsp56004 user? manual 4-3 4.1 introduction the external memory interface (emi) enables the dsp to access external dynamic and/or static memory with no (or minimal) additional logic. the emi permits simple implementation of data-delay buffers in external memory and is often used for audio sample storage, as required by digital reverberation algorithms. the emi is designed to connect directly to one or two page-mode dram devices of the following sizes: 64 k 4, 256 k 4, 1 m 4, and 4 m 4 bits. when using srams, the emi can directly access up to 256 k 8 bits. the data bus width can be 4- or 8-bits wide. data words of 8-, 12-, 16-, 20- or 24-bits can be stored and retrieved via the emi with automatic packing and unpacking. in addition, the emi can be configured to operate in the absolute addressing mode. this allows connection to external memory devices for program bootstrap and data storage, as well as general parallel access to external memory-mapped peripheral devices. 4.1.1 theory of operation the dsp views the emi as a memory-mapped peripheral. the emi functions as a memory-mapped peripheral in which data transfers are performed by moving data to/from data registers, and control is exercised by polling status flags in the control/status register or by servicing interrupts. an external memory write is executed by writing the data into the emi data write register (edwr). this will trigger the emi operation in which the edwr contents are transferred to the external memory device. the edwr is free for the next write operation when signalled by a status bit or by an interrupt request. an external memory read is triggered by either writing to the emi offset register (eor) or reading the emi data read register (edrr). this will trigger an emi read operation in which the data is read from the external memory device and is stored in the edrr. the end of operation is signaled by a status bit or by an interrupt request. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-4 dsp56004 user? manual motorola external memory interface introduction 4.1.2 emi features the main features of the emi are: direct connection to several possible memory device configurations: one or two dram devices of 64 k 4, 256 k 4, 1 m 4 or 4 m 4 bits sram addressing with one device select and 256 k address range sram addressing with two device selects and 128 k address range sram addressing with four device selects and 32 k address range additional sram or peripheral addressing with address range of 32 k data bus can be 4 or 8 bits wide data words can be 8, 12, 16, 20 or 24 bits long automatic data pack/unpack to fit and orient external bus width and external word length to internal 24-bit word format programmable timing features: independently selectable timing for sram or dram automatic dram refresh by internal refresh timer two timing modes for dram, sixteen timing modes for sram address features: relative addressing for data-delay buffers dram absolute addressing for efficient data storage absolute addressing for program bootstrap and overlays (sram or eprom), and to access external peripherals two base registers to handle two delay buffers in parallel base-offset address calculation for data-delay buffers optional base address post update (increment) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-5 4.2 emi programming model the emi registers available to the programmer are shown in figure 4-1 on page 4-6. all accessible registers are mapped into the internal i/o memory space. these registers can be accessed through regular move instructions or by peripheral move (movep) instructions. the registers are described in the following sections. the interrupt vector table for the emi is shown in table 4-1 . the interrupts generated by the emi are prioritized, as shown in table 4-2 . since either a read condition or a write condition (but not both) can trigger an interrupt, the read data and write data interrupts share the same level of priority. table 4-1 emi interrupt vector address interrupt source p: $0030 emi write data p: $0032 emi read data p: $0034 emi ebar0 memory wrap p: $0036 emi ebar1 memory wrap table 4-2 emi internal interrupt priorities priority interrupt source highest emi ebar0 memory wrap emi ebar1 memory wrap lowest emi read or write data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-6 dsp56004 user? manual motorola external memory interface emi programming model figure 4-1 emi registers (eor0) x: $ffe9 (eor1) x: $ffed global data bus (gdb) control/status register (ecsr) 0 23 x: $ffeb to emi data bus base address register 0 (ebar0) 0 23 x: $ffe8 data read register (edrr) 0 23 (edrr0) x: $ffea data register buffer (edrb) 0 23 refresh control register (ercr) 0 23 x: $ffef base address register 1 (ebar1) 0 23 x: $ffec offset register (eor) 0 23 data write register (edwr) 0 23 (edwr1) x: $ffee (edrr1) x: $ffee (edwr0) x: $ffea write offset register (ewor) 0 23 x: $fff6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-7 4.2.1 emi base address registers (ebar0 and ebar1) the read/write 24-bit emi base address registers (ebar0 and ebar1) contain the base address used by the emi to calculate the address (in external memory) of the word to be accessed. during a read access, the word address is formed by subtracting the value in the eor from the value in either ebar0 or ebar1 (ebarx). during a write access, the word address is formed by subtracting the contents of the write offset register (ewor) from the contents of ebarx. the ebarx contents can be incremented after the memory access. the increment operates on all 24 bits of ebarx. the base address is stored in 24-bit unsigned integer format. 4.2.2 emi write offset register (ewor) the read/write 24-bit emi write offset register (ewor) is used by the emi to calculate the address (in external memory) of the word to be accessed during write operations. the address is formed by subtracting the contents of the ewor from the contents of ebarx. the offset is stored in 24-bit unsigned integer format. the ewor contains a displacement value (from the start of the data-delay buffer) and is used to access a delayed data sample location. for example, assuming that ebarx points to the sample at time 0, then in order to write the data sample delayed by n, the value of n should be written into the ewor. note: the ewor is cleared by hardware reset and software reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-8 dsp56004 user? manual motorola external memory interface emi programming model 4.2.3 emi offset register (eor) the emi uses the read/write 24-bit emi offset register (eor) to calculate the address (in external memory) of the word to be accessed during read operations. the eor is a single 24-bit register that is mapped to two different memory locations (eor0 and eor1). the address is formed by subtracting the contents of the eor from the contents of ebarx. the offset is stored in 24-bit unsigned integer format. the eor contains a displacement value (from the start of the data-delay buffer) and is used to access delayed data samples. for example, assuming that ebarx points to the sample at time 0, then to read the data sample delayed by n, the value of n is written into the eor. the eor has two addresses: $xffe9 (eor0) and $xffed (eor1). when the ecsr emi read trigger select (erts) bit (see figure 4-2 ) is cleared, writing to eor0 triggers an emi memory read operation that will use the value in the eor and the value in the ebar0 for address calculation. writing to eor1 when the erts bit is cleared triggers an emi memory read operation that will use the values in the eor and the ebar1 for address calculation. the eor is cleared by hardware reset and software reset. see section 4.2.5 emi data read register (edrr) on page 4-9 for a description of operation when the erts bit is set. figure 4-2 emi control/status register (ecsr) ewl1 edwe ebw 0 1 2 eam1 3 eam2 4 5 6 7 8 9 10 11 ewl0 12 13 14 estm1 15 16 17 18 19 20 21 22 23 eam0 ebsy ebdf eme erts estm0 edtm estm2 estm3 edrf eis0 einr einw eis1 eam3 emwie ewl2 emi data bus width emi data word length emi addressing mode increment ebar (read) increment ebar (write) read/write interrupt select memory-wrap interrupt enable edwr empty edrr full edrb & edrr full emi busy status emi data word length emi read trigger select emi dram timing emi sram timing emi enable aa0402 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-9 4.2.4 emi data write registers (edwr) the emi data write register (edwr) is a single 24-bit write-only register that is mapped to two memory addresses and is used when writing data to memory. data to be transferred to external memory is written into either edwr0 or edwr1. the contents of the written register are transferred to the data register buffer for memory writes. all transfers to/from edwr0 or edwr1 are 24-bit transfers. writing to edwr0 ($ffea) triggers an emi memory write operation that will use ebar0 and ewor to generate the word address. writing to edwr1 ($ffea) triggers an emi memory write operation that will use ebar1 and ewor to generate the word address. 4.2.5 emi data read register (edrr) the emi data read register (edrr) is a single 24-bit read-only register that is mapped to two memory addresses and is used when reading data from memory. data to be received from external memory arrives in the edrr, and can be read from either the $ffea (edrr0) or the $ffee (edrr1) memory location. the contents of the data register buffer are transferred to the edrr at the end of a memory read if the edrr is empty. all transfers to/from the edrr are 24-bit transfers. reading edrr0 ($ffea) when the erts bit (in the ecsr) is set triggers an emi memory read operation that will use ebar0 and eor to generate the word address. reading edrr1 when the erts bit (in the ecsr) is set triggers an emi memory read operation that will use ebar1 and eor to generate the word address. see section 4.2.3 emi offset register (eor) on page 4-8 for a description of the operation when erts is cleared. 4.2.6 emi data register buffer (edrb) data pack and unpack procedures during memory accesses are performed in the 24-bit emi data register buffer (edrb). since the emi data bus is either 4- or 8-bits wide and the words for transfer are 8-, 12-, 16-, 20-, or 24-bits wide, the data word must be sliced (unpacked) into data-bus-width segments for storage in memory, or must be packed when reading memory. when writing 8-bit or 16-bit words to external memory, only the most significant 8 or 16 bits of the edrb contents are transferred. when reading 8-bit or 16-bit words from external memory, the words are left-aligned and zero-extended (to the right) before being transferred to the edrr. when writing 12-bit or 20-bit words to external memory via a 4-bit data bus, only the most significant 12 or 20 bits of the edrb contents are transferred. similarly, when f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-10 dsp56004 user? manual motorola external memory interface emi programming model reading 12-bit or 20-bit words from external memory via a 4-bit data bus, the words are left-aligned and zero-extended to the right before being transferred to the edrr. when 12-bit or 20-bit words are transferred via 8-bit data bus, 16 or 24 bits, are transferred in both read and write directions. while packing or unpacking, the data word is held in the edrb. during memory writes, the data to be written is transferred from the edwr to the edrb for unpacking. the edrb cannot be accessed by the dsp directly. 4.2.7 emi control/status register (ecsr) the emi control/status register (ecsr) is a 24-bit read/write register used by the dsp to control and interrogate the emi operation. the ecsr bits are shown in figure 4-2 and described in the following paragraphs. note: if ecsr control bits are changed while the emi is busy (with the exception of the ecsr interrupt controls emwie, eis[1:0], and the read trigger select erts), improper operation can result. 4.2.7.1 emi data bus width (ebw)?it 0 the read/write control bit emi data bus width (ebw) defines the width of the emi data bus. when ebw is cleared (ebw = 0), the data bus is 4 bits wide. when ebw is set (ebw = 1), the data bus is 8 bits wide. the bus width affects the number of memory accesses and address generation required for a data word transfer. the number of memory accesses performed by the emi during a word transfer and the number of memory locations required for a word storage (for words of different lengths), in both relative and absolute addressing modes, is shown in table 4-3 . note: ebw is cleared by hardware reset and software reset. table 4-3 emi memory accesses and locations per word addressing bus width word length memory locations/ word memory accesses/ word relative 4 8 2 2 relative 4 12 4 3 relative 4 16 4 4 relative 4 20 8 5 relative 4 24 8 6 relative 4 16 data/24 address 8 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-11 4.2.7.2 emi word length (ewl[2:0])?its 16,2, and 1 the read/write control bits emi word length (ewl[2:0]) select the length of the data word to be transferred. the encoding of ewl[2:0] is shown in table 4-4 . note: ewl[2:0] are cleared by hardware reset and software reset. relative 8 8 1 1 relative 8 12 2 2 relative 8 16 2 2 relative 8 20 4 3 relative 8 24 4 3 relative 8 16 data/24 address 4 2 absolute 4 8 2 2 absolute 4 12 3 3 absolute 4 16 4 4 absolute 4 20 5 5 absolute 4 24 6 6 absolute 4 16 data/24 address 4 4 absolute 8 8 1 1 absolute 8 12 2 2 absolute 8 16 2 2 absolute 8 20 3 3 absolute 8 24 3 3 absolute 8 16 data/24 address 2 2 table 4-4 emi word length ewl2 ewl1 ewl0 word length 0 0 0 8-bit data word 0 0 1 16-bit data word table 4-3 emi memory accesses and locations per word (continued) addressing bus width word length memory locations/ word memory accesses/ word f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-12 dsp56004 user? manual motorola external memory interface emi programming model 4.2.7.3 emi addressing mode (eam[3:0])?its 6? the read/write emi addressing mode (eam[3:0]) control bits select the addressing mode of the emi. the addressing modes are shown in table 4-5 . the values in eam[3:0] select which functions will be performed by the emi pins and if the device being accessed is an sram or dram. note: eam[3:0] are cleared by hardware reset and software reset. 0 1 0 24-bit data word 0 1 1 16-bit data word/24-bit data addressing 1 0 0 reserved 1 0 1 12-bit data word 1 1 0 20-bit data word 1 1 1 reserved table 4-5 emi addressing modes eam [3:0] type addressing address lines chip select ras/ cas address range 0000 1,2 sram absolute ma[14:0] none refresh only 32 k 0001 sram relative ma[17:0] mcs0 n.a. 256 k 0010 sram relative ma[16:0] mcs [1:0] n.a. 256 k 0011 sram relative ma[14:0] mcs [3:0] n.a. 128 k 0100 dram relative ma[7:0] na yes 64 k 0101 dram relative ma[8:0] na yes 256 k 0110 dram relative ma[9:0] na yes 1 m 0111 dram relative ma[10:0] na yes 4 m 10xx reserved 1100 2 dram absolute ma[7:0] na yes 64 k table 4-4 emi word length (continued) ewl2 ewl1 ewl0 word length f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-13 the maximum number of word locations that can be stored in the external memory when using the sram addressing modes is shown in table 4-6 . the maximum number of word locations that can be stored in the external memory when using the dram, in both relative and absolute addressing modes, is shown in table 4-7 on page 4-14 and table 4-8 on page 4-15. when using the 16-bit word length with 24-bit addressing (ewl[2:0] = 011), the number of available word locations is the same as those for 16-bit word length in the absolute addressing modes and the same as those for 24-bit length in the relative addressing modes. 1101 2 dram absolute ma[8:0] na yes 256 k 1110 2 dram absolute ma[9:0] na yes 1 m 1111 2 dram absolute ma[10:0] na yes 4 m note: 1. in this mode, mcs0 and ma15 are held high. mras and mcas , if enabled, are active only during dram refresh cycles. devices to be addressed using this mode should be enabled with some hardware external to the emi, such as a gpio pin. 2. in the absolute addressing modes, if post-increment of ebar is enabled and multiple memory accesses are required for a word transfer, ebar will be incremented after each memory access. table 4-6 emi maximum sram size eam[3:0] bus width word length number of words 0000 4 8 16 k 0000 4 12 10,922 0000 4 16 8 k 0000 4 20 6,553 0000 4 24 5,461 0000 8 8 32 k 0000 8 12 or 16 16 k 0000 8 20 or 24 10,922 0001 and 0010 4 8 128 k table 4-5 emi addressing modes (continued) eam [3:0] type addressing address lines chip select ras/ cas address range f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-14 dsp56004 user? manual motorola external memory interface emi programming model 0001 and 0010 4 12 or 16 64 k 0001 and 0010 4 20 or 24 32 k 0001 and 0010 8 8 256 k 0001 and 0010 8 12 or 16 128 k 0001 and 0010 8 20 or 24 64 k 0011 4 8 64 k 0011 4 12 or 16 32 k 0011 4 20 or 24 16 k 0011 8 8 128 k 0011 8 12 or 16 64 k 0011 8 20 or 24 32 k table 4-7 emi maximum dram size (relative addressing) eam[3:0] bus width word length dram devices number of words 0100 4 8 64 k 4 32 k 0100 4 12 or 16 64 k 4 16 k 0100 4 20 or 24 64 k 4 8 k 0100 8 8 2 64 k 4 64 k 0100 8 12 or 16 2 64 k 4 32 k 0100 8 20 or 24 2 64 k 4 16 k 0101 4 8 256 k 4 128 k 0101 4 12 or 16 256 k 4 64 k 0101 4 20 or 24 256 k 4 32 k 0101 8 8 2 256 k 4 256 k 0101 8 12 or 16 2 256 k 4 128 k table 4-6 emi maximum sram size (continued) eam[3:0] bus width word length number of words f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-15 0101 8 20 or 24 2 256 k 4 64 k 0110 4 8 1 m 4 512 k 0110 4 12 or 16 1 m 4 256 k 0110 4 20 or 24 1 m 4 128 k 0110 8 8 2 1 m 4 1 m 0110 8 12 or 16 2 1 m 4 512 k 0110 8 20 or 24 2 1 m 4 256 k 0111 4 8 4 m 4 2 m 0111 4 12 or 16 4 m 41 m 0111 4 20 or 24 4 m 4 512 k 0111 8 8 2 4 m 44 m 0111 8 12 or 16 2 4 m 42 m 0111 8 20 or 24 2 4 m 41 m table 4-8 emi maximum dram size (absolute addressing) eam[3:0] bus width word length dram devices number of words 1100 4 8 64 k 4 32 k 1100 4 12 64 k 4 21,845 1100 4 16 64 k 4 16 k 1100 4 20 64 k 4 13,107 1100 4 24 64 k 4 10,922 1100 8 8 2 64 k 4 64 k 1100 8 12 or 16 2 64 k 4 32 k 1100 8 20 or 24 2 64 k 4 21,845 1101 4 8 256 k 4 128 k 1101 4 12 256 k 4 87,381 1101 4 16 256 k 4 64 k 1101 4 20 256 k 4 52,428 table 4-7 emi maximum dram size (relative addressing) (continued) eam[3:0] bus width word length dram devices number of words f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-16 dsp56004 user? manual motorola external memory interface emi programming model 4.2.7.4 emi increment ebar after read (einr)?it 7 the read/write control bit emi increment ebar after read (einr) enables the function of incrementing the contents of the relevant ebarx after a read operation. if einr is cleared, ebarx will not be modified after read operations. if einr is set, the contents of ebarx will be incremented by one after generating the address for the read operation. this bit affects all operating modes. note: einr is cleared by hardware reset and software reset. 4.2.7.5 emi increment ebar after write (einw)?it 8 the read/write control bit emi increment ebar after write (einw) enables the function of incrementing the contents of the relevant ebarx after a write operation. 1101 4 24 256 k 4 43,690 1101 8 8 2 256 k 4 256 k 1101 8 12 or 16 2 256 k 4 128 k 1101 8 20 or 24 2 256 k 4 87,381 1110 4 8 1 m 4 512 k 1110 4 12 1 m 4 349,525 1110 4 16 1 m 4 256 k 1110 4 20 1 m 4 209,715 1110 4 24 1 m 4 174,762 1110 8 8 2 1 m 41 m 1110 8 12 or 16 2 1 m 4 512 k 1110 8 20 or 24 2 1 m 4 349,525 1111 4 8 4 m 42 m 1111 4 12 4 m 4 1,398,101 1111 4 16 4 m 41 m 1111 4 20 4 m 4 838,860 1111 4 24 4 m 4 699,050 1111 8 8 2 4 m 44 m 1111 8 12 or 16 2 4 m 42 m 1111 8 20 or 24 2 4 m 4 1,398,101 table 4-8 emi maximum dram size (absolute addressing) (continued) eam[3:0] bus width word length dram devices number of words f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-17 if einw is cleared, ebarx will not be modified after write operations. if einw is set, the contents of ebarx will be incremented by one after generating the address for the write operation. this bit affects all operating modes. einw is cleared by hardware reset and software reset. 4.2.7.6 emi interrupt select (eis[1:0])?its 9?0 the read/write emi interrupt select (eis[1:0]) control bits are used to select the condition that will trigger an emi read/write interrupt. when eis[1:0] = 00, emi read and write interrupts are disabled. when eis[1:0] = 01, a write-interrupt vector will be generated when the edwr becomes empty (edwe = 1). when eis[1:0] = 10, a read-interrupt vector will be generated when the edrr becomes full (edrf = 1). when eis[1:0] = 11, a read- interrupt vector will be generated when both the edrb and the edrr are full (ebdf = 1). table 4-9 summarizes the functionality of the interrupt select bits. note: eis[1:0] are cleared by hardware reset and software reset. note: clearing eis[1:0] will mask pending emi interrupts, but after a one-instruction-cycle delay. if eis[1:0] are cleared in a long interrupt service routine, it is recommended that at least one other instruction should separate the instruction that clears eis[1:0] and the rti instruction at the end of the interrupt service routine. 4.2.7.7 emi memory-wrap interrupt enable (emwie)?it 11 the read/write control bit emi memory-wrap interrupt enable (emwie) enables interrupts when the relevant ebar is incremented by one (controlled by einr and einw) and wrapped around from the largest word address in the pre-programmed memory space. when emwie is cleared, memory-wrap interrupts are disabled. when emwie is set, memory-wrap interrupts are enabled with separate interrupt vectors for each of ebar0 and ebar1. the largest word address is reached when the value of the significant bits in ebarx is all 1s. the number of the significant bits in ebarx involved with address generation can be concluded from table 4-13 table 4-9 emi read/write interrupt select eis1 eis0 word length 0 0 read and write interrupts disabled 0 1 write interrupt enabled 1 0 read interrupt enabled if edrf = 1 1 1 read interrupt enabled if ebdf = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-18 dsp56004 user? manual motorola external memory interface emi programming model on page 4-26, table 4-15 on page 4-29, and table 4-16 on page 4-31, always starting at a0 and ignoring the relative addressing extension bits. the memory-wrap interrupt is generated when the significant bits in ebarx change from all 1s to all 0s following the ebarx post-increment, for any particular selection of addressing mode, word length, and bus width. for example, it can be seen from table 4-16 that for a selection of eam[3:0] = 1101 there are 18 significant bits in ebarx (a[17:0]) that determine the word address, therefore, in this case an ebarx memory-wrap interrupt is generated when the 18 least significant bits (lsbs) in ebarx change from all 1s to all 0s as a result of the ebarx post-increment operation. similarly, for a selection of eam[3:0] = 0101, ewl[2:0] = 001 and ebw = 0 there are 16 significant bits in ebarx (a[15:0]) that determine the word address. note: when einr and einw bits are cleared, memory-wrap interrupts cannot be generated since no ebarx is post-incremented. emwie is cleared by hardware or software reset. 4.2.7.8 emi data write register empty (edwe)?it 12 the emi data write register empty (edwe) read-only status bit indicates the state of the edwr. edwe is set (edwr empty) by the emi controller when transferring a data word from the edwr to the edbr during a memory write operation. edwe is cleared (edwr full) when data is written into the edwr when starting a memory write operation. note: edwe is set by hardware reset, software reset, individual reset, and while the device is in the stop state. 4.2.7.9 emi data read register full (edrf)?it 13 the emi data read register full (edrf) read-only status bit indicates the state of the edrr. edrf is set (edrr full) by the emi controller when transferring a data word from the edrb to the edrr at the end of a memory read operation. note: edrf is cleared (edrr empty) when edrr is read by the dsp core.edrf is also cleared by hardware reset, software reset, individual reset, and while the device is in the stop state. 4.2.7.10 emi data register buffer and data read register full (ebdf)?it 14 the emi data register buffer and data read register full (ebdf) read-only status bit indicates the status of the edrb and edrr during read operations. ebdf is set when both the edrb and the edrr contain data after memory read operations. ebdf is cleared otherwise. note: ebdf is cleared by hardware reset, software reset, individual reset, and while the dsp is in the stop state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-19 4.2.7.11 emi busy (ebsy)?it 15 the emi busy (ebsy) read-only status bit indicates the emi state. ebsy is set when the emi is busy transferring data or when there is a pending transfer request. ebsy is cleared when no transfers currently are being done and no requests are pending. note: ebsy is cleared by hardware reset, software reset, individual reset, and while the dsp is in the stop state. 4.2.7.12 emi read trigger select (erts)?it 17 the read/write emi read trigger select (erts) control bit selects the trigger event for read operations. when erts is cleared, read operations are triggered by a write to the eor. when erts is set, read operations are triggered by reading the edrr. note: erts is cleared by hardware reset and software reset. 4.2.7.13 emi dram memory timing (edtm)?it 18 the read/write emi dram memory timing (edtm) control bit selects the emi dram timing mode of operation. when edtm is set, emi dram mode accesses and dram refresh cycles operate in the slow timing mode. when edtm is cleared, emi dram mode accesses and dram refresh cycles operate in the fast timing mode. the edtm bit does not affect the timing of sram accesses. see section 4.8 emi timing for more detailed information. note: edtm is set by hardware reset and software reset. table 4-10 emi dram timing (clock cycles per word transfer) addressing word length bus width edtm = 1 (slow) edtm = 0 (fast) relative 8 4 16 11 relative 8 8 12 8 relative 12 4 20 14 relative 16 4 24 17 relative 12 or 16 8 16 11 relative 20 4 28 20 relative 24 4 32 23 relative 20 or 24 8 20 14 absolute 8 4 2 12 = 24 2 8 = 16 absolute 8 8 1 12 = 12 1 8 = 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-20 dsp56004 user? manual motorola external memory interface emi programming model 4.2.7.14 emi sram memory timing (estm[3:0])?bits 19?2 the read/write emi sram memory timing (estm[3:0]) control bits select the emi sram timing mode of operation. the estm[3:0] bits do not affect the timing of dram mode accesses or of dram refresh cycles. see section 4.8 emi timing for more detailed information. note: estm[3:0] are set by hardware reset and software reset. absolute 12 4 3 12 = 36 3 8 = 24 absolute 16 4 4 12 = 48 4 8 = 32 absolute 12 or 16 8 2 12 = 24 2 8 = 16 absolute 20 4 5 12 = 60 5 8 = 40 absolute 24 4 6 12 = 72 6 8 = 48 absolute 20 or 24 8 3 12 = 36 3 8 = 24 refresh cycle 13 9 table 4-11 emi sram timing (clock cycles per word transfer) word length bus width clock cycles 842 (4 + estm) 881 (4 + estm) 12 4 3 (4 + estm) 16 4 4 (4 + estm) 12 or 16 8 2 (4 + estm) 20 4 5 (4 + estm) 24 4 6 (4 + estm) 20 or 24 8 3 (4 + estm) where estm is the value of the estm[3:0] bits, ranging from 0 to 15 table 4-10 emi dram timing (clock cycles per word transfer) (continued) addressing word length bus width edtm = 1 (slow) edtm = 0 (fast) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi programming model motorola dsp56004 user? manual 4-21 4.2.7.15 emi enable (eme)?it 23 the read/write control bit emi enable (eme) enables the emi for data-transfer operations. when eme is set, the emi accepts data transfer triggers and executes data transfers. when eme is cleared, the emi enters the individual reset state, that is, the emi is disabled for data transfers and the status flags in the ecsr are reset to the same states as during hardware reset. when eme is cleared, the emi pins are reset to the state defined in section 2: pin descriptions but the control bits are unaffected. the individual reset state is entered one instruction cycle after clearing eme. dram refresh operation, if previously enabled, will continue while the emi is in the individual reset state. note: eme is cleared by hardware reset and software reset. 4.2.8 emi refresh control register (ercr) the emi refresh control register (ercr) is a 24-bit read/write register used to control the refresh of dram memories. refresh can only occur while the emi is set to work with dram memories (eam[3:0] = x1xx) or while in the sram absolute addressing mode (eam[3:0] = 0000). the ercr is cleared by hardware reset and software reset. the ercr bits are shown in figure 4-3 and are described in the following paragraphs. figure 4-3 emi refresh control register (ercr) 0 1 2 3 4 5 6 7 8 9 10 11 reserved bit 12 13 14 15 16 17 18 19 20 21 22 23 eref ered eps0 ecd0 ecd3 ecd4 ecd1 ecd2 eps1 eosr ecd6 ecd7 ecd5 prescaler rate one-shot refresh refresh enable(debug) refresh enable refresh rate aa0295 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-22 dsp56004 user? manual motorola external memory interface emi programming model 4.2.8.1 emi refresh clock divider (ecd[7:0])?its 0? the read/write emi refresh clock divider (ecd[7:0]) bits are used to preset an 8-bit counter that generates the dram refresh requests (if dram refresh is enabled). the counter itself is not accessible to the user. when the counter reaches zero, it is reloaded from the ecd[7:0] bits. the divide rate range is between 1 (ecd[7:0]= $00) and 256 (ecd[7:0] = $ff). note: the ecd[7:0] bits are cleared by hardware reset and software reset. 4.2.8.2 ercr reserved bits?its 8?7, 21 these bits in the ercr are reserved and unused. they read as 0s and should be written with 0s for future compatibility. 4.2.8.3 emi refresh clock prescaler (eps[1:0])?its 18?9 the read/write emi refresh clock prescaler (eps[1:0]) bits control a prescaler that is connected in series with the refresh clock divider. these bits are used to extend the range of the refresh clock divider when a slower refresh clock rate is desired. when eps[1:0] = 00, a divide-by-64 prescaler is connected in series with the refresh clock divider. when eps[1:0] = 01, a divide-by-8 prescaler is connected in series with the refresh clock divider. when eps[1:0] = 10, the prescaler is bypassed. eps[1:0] = 11 is reserved for future expansion. note: the eps[1:0] bits are cleared by hardware reset and software reset. 4.2.8.4 emi one-shot refresh (eosr)?it 20 the read/write emi one-shot refresh (eosr) bit is used to trigger one dram refresh cycle under software control. when eosr is set, one column address strobe (cas ) before row address strobe (ras ) refresh cycle is generated, independent of the state of bits eref and ered (see below). the eosr bit is automatically cleared by the emi hardware after the refresh cycle has been generated. the refresh cycle will be generated immediately if no word transfer is occurring, or at the end of the current word access if a word transfer is in progress. note: the eosr bit is cleared by hardware reset and software reset. 4.2.8.5 emi refresh enable when debugging (ered)?it 22 the read/write control bit emi refresh enable when debugging (ered) is used to enable dram refresh cycles when the dsp enters debug mode if eref is cleared. when ered is set, cas before ras refresh cycles are inserted between data word transfers while the dsp is in the debug mode independent of the state of eref. refresh cycle requests are generated according to the output clock rate of the refresh timer. if ered is cleared, refresh cycle insertion is disabled when the dsp leaves the debug mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi address generation motorola dsp56004 user? manual 4-23 note: the ered bit is cleared by hardware reset and software reset. 4.2.8.6 ercr refresh enable (eref)?it 23 the read/write control bit eref is used to enable dram refresh cycles. when set, cas before ras refresh cycles are inserted between data word transfers for both regular dsp operation and if the dsp is in the debug mode. refresh cycle requests are generated according to the output clock rate of the refresh timer. if eref is cleared, refresh cycle insertion is disabled. note: the eref bit is cleared by hardware reset and software reset. 4.3 emi address generation address generation for external memory accesses is done by the emi in the address generation unit (agu). a block diagram of the agu is shown in figure 4-4 . the agu forms a word address for a read operation by subtracting the contents of the eor from the contents of the appropriate ebar. for a write operation, the word address is formed by subtracting the contents of the ewor from the contents of the appropriate ebar. the word address must then be transformed into one or more physical addresses as required for loading/storing the data word. the mapping from word address to physical addresses is described in the following sections. the base address register in use can be optionally incremented by one after calculating the word address. figure 4-4 emi address generation block diagram base address offset register 24 24 24 alu address format emi address and chip select pins c2?0 word address: a23?0 3 +1 relative addressing extension bits conversion aa0296 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-24 dsp56004 user? manual motorola external memory interface emi address generation when using the sram or dram relative addressing modes, the physical addresses are generated by the address format conversion circuit after appending extension bits to the right of the word address. table 4-12 shows the extension bits used for every possible combination of word length and bus width, the number of accesses required (equal to the number of physical addresses generated) and the states that the extension bits run through during the accesses. 4.3.1 sram absolute addressing the sram absolute addressing mode is selected when eam[3:0] = 0000. in this addressing mode, the physical address is formed by writing the 15 lsbs of the calculated word address (a[14:0]) directly to the ma[14:0] address pins. the a[23:15] portion of the word address is ignored. no extension bits are used in the physical address generation. ma15 and mcs0 are held high. if more than one physical address must be accessed to complete the word transfer, ebarx must be post-incremented by one after each physical address access, otherwise the same physical address will be accessed more than once. in this case, it is required that the appropriate control bit be set in the ecsr (einr for reads, einw for writes). the emi will execute the series of accesses required, incrementing ebarx after each access, packing (during a read operation) or unpacking (during a write operation) the data word segment. the accesses proceed from the least significant to the most significant portion of the word. for each of the accesses, the contents of table 4-12 relative addressing extension bits word length bus width no. access running order active extension bits 8 4-bit 2 0,1 c0 8 8-bit 1 none none 12 4-bit 3 01, 10, 11 c1, c0 16 4-bit 4 00, 01, 10,11 c1, c0 12 or 16 8-bit 2 0,1 c0 20 4-bit 5 011, 100, 101, 110, 111 c2, c1, c0 24 4-bit 6 010, 011, 100, 101, 110, 111 c2, c1, c0 20 or 24 8-bit 3 01, 10, 11 c1, c0 16 (24 address) 4-bit 4 100, 101, 110,111 c2, c1, c0 16 (24 address) 8-bit 2 10, 11 c1, c0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi address generation motorola dsp56004 user? manual 4-25 ebarx and eor are written to the alu. the contents of ebarx or eor should not be changed during word transfers. the sram absolute addressing mode is useful when accessing external peripherals or memories that contain program segments, cases where it is important to have a one-to-one correspondence between the word address and the external physical location. this mode can be used concurrently with either the sram relative addressing or the dram relative addressing; that is, it is possible to access static memory devices or peripherals using the absolute addressing mode while having data-delay buffers implemented in either sram or dram memories. note that it is assumed that the device select for the devices being addressed with the absolute addressing mode is provided by circuits that are external to the emi, such as a gpio signal. while in the sram absolute addressing mode, refresh of drams connected to the emi will continue if the refresh is enabled in the ercr. 4.3.2 sram relative addressing the sram relative addressing modes (eam[3:0] = 0001, 0010, 0011) are used to implement data-delay buffers in sram. in this addressing mode, the physical addresses required are formed by taking some lsbs of the calculated word address and appending from 0 to 3 extension bits to the right of the word address (forming the lsbs of the physical address). the extension bits are then used to generate the number of physical addresses required. when eam[3:0]= 0001, it is possible to connect directly a single 4-bit or 8-bit wide sram device of up to 256 k addresses, since only mcs0 is active for any access. when eam[3:0] = 0010, it is possible to connect directly up to two 4-bit or 8-bit wide sram devices with up to 128 k addresses each, since mcs0 and mcs1 are active. when eam[3:0] = 0011, it is possible to connect directly up to four 4-bit or 8-bit wide sram devices with up to 32 k addresses each, since mcs0 , mcs1 , mcs2 , and mcs3 are active. note: in this addressing mode, if the word length is 20 bits or 24 bits (or 16 bits using 24-bit addressing), it is possible to connect only three srams (and save memory), since mcs0 will not be activated at all. table 4-13 summarizes the address generation for the sram addressing modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-26 dsp56004 user? manual motorola external memory interface emi address generation table 4-13 word address to physical address mapping for sram eam [3:0] sram max size ewl [2:0] ebw mcs0 mras mcas ma15 ma [14:0] 0000 1 32 k xx x high mras mcas high a [14:0] 0001 1 256 k 000 0 low a16 a15 a14 a [13:0], c0 1 low a17 a16 a15 a [14:0] x01 0 low a15 a14 a13 a[12:0], c0, c1 1 low a16 a15 a14 a[13:0], c0 x1x 0 low a14 a13 a12 a[11:0], c0,c1, c2 1 low a15 a14 a13 a[12:0], c0, c1 0010 2 128 k 000 0 mcs0 = c0 mcs1 = c0 a16 a15 a [14:0] 1 mcs0 = a0 mcs1 = a0 a17 a16 a [15:1] x01 0 mcs0 = c1 mcs1 = c1 a15 a14 a[13:0], c0 1 mcs0 = c0 mcs1 = c0 a16 a15 a [14:0] x1x 0 mcs0 = c2 mcs1 = c2 a14 a13 a[12:0], c0, c1 1 mcs0 = c1 mcs1 = c1 a15 a14 a[13:0], c0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi address generation motorola dsp56004 user? manual 4-27 4.3.3 dram relative addressing the dram relative addressing modes (eam[3:0] = 01xx) are used when implementing data-delay buffers in dram. in dram relative addressing, each word access is translated into physical addresses by first generating the row address and then following with one or more column addresses. the row access is an out-of-page (i.e., slow) access, while the subsequent column accesses are in-page (i.e., fast) accesses. the row address is formed by taking part of the calculated word address (the number of bits will be determined by the number of rows in the dram). the column addresses are generated by taking the remaining bits of the word address and appending from 0 to 3 extension bits to the right (forming the lsbs of the column addresses). the extension bits are then used to generate the number of column addresses required. address pins that are not required are kept at the 0011 4 32 k 000 0 a [15:1] 1 a [16:2] x01 0 a [14:0] 1 a [15:1] x1x 0 a[13:0], c0 1 a [14:0] table 4-13 word address to physical address mapping for sram (continued) eam [3:0] sram max size ewl [2:0] ebw mcs0 mras mcas ma15 ma [14:0] mcs0 = a0 & c0 mcs1 = a0 & c0 mcs2 = a0 & c0 mcs3 = a0 & c0 mcs0 = a1 & c0 mcs1 = a1 & a0 mcs2 = a1 & a0 mcs3 = a1 & a0 mcs0 = c0 & c1 mcs1 = c0 & c1 mcs2 = c0 & c1 mcs3 = c0 & c1 mcs0 = a0 & c0 mcs1 = a0 & c0 mcs2 = a0 & c0 mcs3 = a0 & c0 mcs0 = c1 & c2 mcs1 = c1 & c2 mcs2 = c1 & c2 mcs3 = c1 & c2 mcs0 = c0 & c1 mcs1 = c0 & c1 mcs2 = c0 & c1 mcs3 = c0 & c1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-28 dsp56004 user? manual motorola external memory interface emi address generation low-logic level. device select pins are deasserted. table 4-14 describes the word-address-to-physical-address mapping for dram. table 4-15 on page 4-29 summarizes the address generation for dram relative addressing. table 4-14 word-address-to-physical-address mapping for dram eam [2:0] dram size row/ col ewl [1:0] ebw ma10 ma9 ma8 ma7 ma[6:3] ma2 ma1 ma0 100 64 k r 00 0 0 0 0 a7 a[6:3] a2 a1 a0 c 0 0 0 a14 a[13:10] a9 a8 c0 c 1 0 0 0 a15 a[14:11] a10 a9 a8 c 01 0 0 0 0 a13 a[12:9] a8 c0 c1 c 1 0 0 0 a14 a[13:10] a9 a8 c0 c 1x 0 0 0 0 a12 a[11:8] c0 c1 c2 c 1 0 0 0 a13 a[12:9] a8 c0 c1 101 256 k r 00 0 0 0 a8 a7 a[6:3] a2 a1 a0 c 0 0 a16 a15 a[14:11] a10 a9 c0 c 1 0 0 a17 a16 a[15:12] a11 a10 a9 c 01 0 0 0 a15 a14 a[13:10] a9 c0 c1 c 1 0 0 a16 a15 a[14:11] a10 a9 c0 c 1x 0 0 0 a14 a13 a[12:9] c0 c1 c2 c 1 0 0 a15 a14 a[13:10] a9 c0 c1 110 1 m r 00 0 0 a9 a8 a7 a[6:3] a2 a1 a0 c 0 a18 a17 a16 a[15:12] a11 a10 c0 c 1 0 a19 a18 a17 a[16:13] a12 a11 a10 c 01 0 0 a17 a16 a15 a[14:11] a10 c0 c1 c 1 0 a18 a17 a16 a[15:12] a11 a10 c0 c 1x 0 0 a16 a15 a14 a[13:10] c0 c1 c2 c 1 0 a17 a16 a15 a[14:11] a10 c0 c1 111 4 m r 00 0 a10 a9 a8 a7 a[6:3] a2 a1 a0 c a20 a19 a18 a17 a[16:13] a12 a11 c0 c 1 a21 a20 a19 a18 a[17:14] a13 a12 a11 c 01 0 a19 a18 a17 a16 a[15:12] a11 c0 c1 c 1 a20 a19 a18 a17 a[16:13] a12 a11 c0 c 1x 0 a18 a17 a16 a15 a[14:11] c0 c1 c2 c 1 a19 a18 a17 a16 a[15:12] a11 c0 c1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi address generation motorola dsp56004 user? manual 4-29 table 4-15 address generation for dram relative addressing eam [3:0] dram size row/ col ewl [2:0] ebw ma10 ma9 ma8 ma7 ma[6:3] ma2 ma1 ma 0 0100 64 k r 0 0 0 a7 a[6:3] a2 a1 a0 c 000 0 0 0 0 a14 a[13:10] a9 a8 c0 c 1 0 0 0 a15 a[14:11] a10 a9 a8 c x01 0 0 0 0 a13 a[12:9] a8 c0 c1 c 1 0 0 0 a14 a[13:10] a9 a8 c0 c x1x 0 0 0 0 a12 a[11:8] c0 c1 c2 c 1 0 0 0 a13 a[12:9] a8 c0 c1 0101 256 k r 0 0 a8 a7 a[6:3] a2 a1 a0 c 000 0 0 0 a16 a15 a[14:11] a10 a9 c0 c 1 0 0 a17 a16 a[15:12] a11 a10 a9 c x01 0 0 0 a15 a14 a[13:10] a9 c0 c1 c 1 0 0 a16 a15 a[14:11] a10 a9 c0 c x1x 0 0 0 a14 a13 a[12:9] c0 c1 c2 c 1 0 0 a15 a14 a[13:10] a9 c0 c1 0110 1 m r 0 a9 a8 a7 a[6:3] a2 a1 a0 c 000 0 0 a18 a17 a16 a[15:12] a11 a10 c0 c 1 0 a19 a18 a17 a[16:13] a12 a11 a10 c x01 0 0 a17 a16 a15 a[14:11] a10 c0 c1 c 1 0 a18 a17 a16 a[15:12] a11 a10 c0 c x1x 0 0 a16 a15 a14 a[13:10] c0 c1 c2 c 1 0 a17 a16 a15 a[14:11] a10 c0 c1 0111 4 m r a10 a9 a8 a7 a[6:3] a2 a1 a0 c 000 0 a20 a19 a18 a17 a[16:13] a12 a11 c0 c 1 a21 a20 a19 a18 a[17:14] a13 a12 a11 c x01 0 a19 a18 a17 a16 a[15:12] a11 c0 c1 c 1 a20 a19 a18 a17 a[16:13] a12 a11 c0 c x1x 0 a18 a17 a16 a15 a[14:11] c0 c1 c2 c 1 a19 a18 a17 a16 a[15:12] a11 c0 c1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-30 dsp56004 user? manual motorola external memory interface emi address generation 4.3.4 dram absolute addressing the dram absolute addressing mode is selected when eam[3:0] = 11xx. in this addressing mode, no extension bits are used in the physical address generation. eam[3:0] = ?100 ?he physical address is formed by multiplexing the sixteen lsbs of the calculated word address (a[15:0]) into the ma[7:0] address pins. the row address is formed by the least significant part (a[7:0]) and the column address is formed by the remaining bits of the word address (a[15:8]). eam[3:0] = ?101 ?he physical address is formed by multiplexing the eighteen lsbs of the calculated word address (a[17:0]) into the ma[8:0] address pins. the row address is formed by the least significant part (a[8:0]) and the column address is formed by the remaining bits of the word address (a[17:9]). eam[3:0] = ?110 ?he physical address is formed by multiplexing the twenty lsbs of the calculated word address (a[19:0]) into the ma[9:0] address pins. the row address is formed by the least significant part (a[9:0]) and the column address is formed by the remaining bits of the word address (a[19:10]). eam[3:0] = ?111 ?he physical address is formed by multiplexing the twenty-two lsbs of the calculated word address (a[21:0]) into the ma[10:0]address pins. the row address is formed by the least significant part (a[10:0]) and the column address is formed by the remaining bits of the word address (a[21:11]). if more than one physical address must be accessed to complete the word transfer, ebarx must be post-incremented by one after each physical address access, otherwise the same physical address will be accessed more than once. to prevent this occurrence, the appropriate ecsr control bit should be set (einr for reads, einw for writes). the emi will execute the series of accesses required, incrementing ebarx after each access, packing (during a read operation) or unpacking (during a write operation) the data word segments. the accesses proceed from the least significant to the most significant portion of the word. for each of the accesses, the contents of ebarx and eor/ewor are written to the alu. the contents of the relevant ebarx and eor/ewor should not be changed during the word transfers. in the dram absolute addressing mode, each physical address access is executed as an independent ?ut-of-page?dram access. as a result, a data word transfer when executed in the dram absolute addressing mode is slower than a transfer executed in the dram relative addressing mode (see table 4-10 on page 4-19). the dram absolute addressing modes, however, are useful when 20- or 24-bit data words are used and the wasted memory locations that appear in the dram relative f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface dram refresh motorola dsp56004 user? manual 4-31 addressing modes are not acceptable. table 4-16 summarizes the address generation for dram absolute addressing. 4.4 dram refresh dram devices require periodic refresh of the data stored in their memory cells (typically every few milliseconds). the emi can carry out dram refresh either by accessing the memory cells frequently enough, or by using dedicated dram refresh accesses. the emi is capable of generating cas before ras refresh cycles automatically or under software control. the refresh cycle insertion rate is controlled by a programmable refresh timer. refer to section 4.4.5 dram refresh timing for more details on dram refresh requirements. there are four ways to refresh a dram memory connected to the emi. the way in which the refresh is achieved has a major influence on the emi real-time performance and on the emi channel bandwidth. 4.4.1 dram refresh without using the internal refresh timer it is possible to refresh the dram by data access itself if a sufficient number of accesses are performed in the required refresh time, and all rows are accessed. this, however, must be assured. the emi address translation is performed in such a way that it is possible to satisfy these requirements by carefully choosing the base addresses of the different data-delay buffers. table 4-16 word-to-physical-address mapping for dram absolute addressing eam[3:0] dram size row/ col ewl [2:0] ebw ma10 ma9 ma8 ma7 ma[6:3] ma2 ma1 ma0 1100 64 k r 0 0 0 a7 a[6:3] a2 a1 a0 c xxx x 0 0 0 a15 a[14:11] a10 a9 a8 1101 256 k r 0 0 a8 a7 a[6:3] a2 a1 a0 c xxx x 0 0 a17 a16 a[15:12] a11 a10 a9 1110 1 m r 0 a9 a8 a7 a[6:3] a2 a1 a0 c xxx x 0 a19 a18 a17 a[16:13] a12 a11 a10 1111 4 m r a10 a9 a8 a7 a[6:3] a2 a1 a0 c xxx x a21 a20 a19 a18 a[17:14] a13 a12 a11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-32 dsp56004 user? manual motorola external memory interface dram refresh the emi physical address is generated using the lsbs of the calculated addresses to represent row addresses, so running sequentially through the address space of a large data buffer during a whole dram refresh cycle should cause a refresh of all of the rows. the time to complete a refresh cycle can be halved by using two data buffers such that their base addresses use different lsbs (row addresses) for half of the required dram row addresses. the user must, however, run through both data buffers sequentially at the same frequency. 4.4.2 dram refresh once port debug mode consideration while the on-chip emulation (once) port is in the debug mode, regular operation of the dsp core is suspended and no regular access to the drams can occur. stored data can therefore be lost. in order to avoid such a situation the user should set the ered bit in the ercr?ee section 4.2.8 emi refresh control register (ercr) . refresh cycles will then be initiated by the internal refresh timer according to the ercr setting. example 4-1 refresh cycle assume that: a 44.1 khz audio sampling frequency is used and the main code loops once every sample period. the external memory has 512 rows (256 k 4 or 8), and needs to refresh all of its rows every 8 ms. two data-delay buffers are used and one access to each buffer is performed in every sample period. the emi increments the base address during each access. the lsbs of the base addresses are chosen as follows: buffer 1: ebar (most significant bits (msbs)) arbitrary; ebar[8:0] = 000000000; buffer 2: ebar (msbs) arbitrary; ebar[8:0] = 100000000; running through 256 sequential locations in both data buffers assures that all the rows are refreshed. the main code loops 352 times in 8 ms, accessing all dram memory locations of the 9 lsbs of the physical address using the incremented addressing mode. since the lsbs of the physical addresses correspond to the row addresses, all rows are refreshed. the same implementation can be extended using 4, 8, or 16 data-delay buffers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface dram refresh motorola dsp56004 user? manual 4-33 4.4.3 using the internal refresh timer refresh cycles can be periodically inserted by the emi. the refresh cycle insertion rate is controlled by the programmable refresh timer. the refresh activity is enabled or disabled according to the eref and ered bits in the ercr and refresh is active only in the emi dram operating modes, or in the concurrent sram mode where the multiplexed pins are defined as cas and ras . the emi always completes its current operation and then checks for pending read or write triggers. the refresh request has the highest priority, otherwise the channel could be kept too busy by the user to ensure all of the dram data is refreshed. the cas before ras refresh cycles are inserted between memory accesses when the emi controller is in its idle state and a refresh request has been delivered by the refresh timer. the refresh request is internally reset at the end of the external refresh cycle. the selected refresh cycle rate must take into account the dsp clock frequency and the dram device refresh requirements. the refresh timer block diagram is illustrated in figure 4-5 . the dsp clock is first divided by a factor ranging between 1 and 256 (according to the ecd bits in ercr), and then by 1, 8, or 64 using a prescaler (selected by bits eps[1:0]), to achieve the required refresh rate. 4.4.3.1 ?n line?refresh during initialization, the user should set the ecsr edtm bit and the ercr bits for the required dram refresh cycle timing, refresh enable (eref), and refresh rate. after this the user does not have to consider refresh cycles, as the internal refresh timer will continuously initiate refresh cycles at the programmed rate. refer to section 4.4.5 for more details. note: special attention should be given to cases in which data transfers are performed when the dsp is not polling status bits or receiving emi interrupts, as the predetermined number of instruction cycles can change due to the insertion of external refresh cycles. figure 4-5 refresh timer functional diagram. f osc divider divide by 1 to 256 ecd[7:0] refresh request rate (dsp clock) divide by 1, 8, or 64 prescaler eps[1:0] aa0297k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-34 dsp56004 user? manual motorola external memory interface dram refresh 4.4.3.2 ?ff line?refresh if the user application has a real-time loop, in which the program initiates external data accesses after which the emi channel is idle, it is possible to use this idle-time window to refresh the dram in a burst manner. this method is useful for real-time applications where data transfers should be performed at maximum speed and the number of instruction cycles per data transfer is critical. during initialization the user should set the ecsr edtm bit and the applicable bits in the ercr for the appropriate dram timing mode and refresh rate. during the time window, when no external data accesses are executed, the user should set the ercr refresh enable bit (eref), turning it off before exiting the time window. when the eref bit is set, the refresh timer will initiate refresh cycles and this bit is cleared once more. care should be taken to ensure that a sufficient number of refresh cycles are executed during the time eref is set. refer to section 4.4.5 for more details. 4.4.3.3 once port debug mode consideration once port operation does not affect the internal refresh timer. no special consideration is necessary when using the ?n line?refresh method. if using the ?ff line?refresh method, however, the execution can stop when the refresh timer is off and data stored in the dram can be lost. in order to avoid this situation, the user should set the ercr ered bit, and refresh cycles will be initiated by the internal refresh timer according to the ercr setting only when the once port is in the debug mode. 4.4.4 software controlled refresh if the user application has a real-time loop, where the program initiates external data accesses after which the emi channel is idle, it is possible to use this idle time window to refresh the dram in a burst manner. this method is useful for real-time applications where data transfers should be performed at maximum speed and the number of instruction cycles-per-data-transfer is critical. during initialization the user should set the ecsr edtm bit (and the applicable bits in the ercr) to select the appropriate dram timing mode and refresh rate. during the time window, when no external data accesses are executed, the user should set the ercr one-shot refresh enable bit (eosr), thus inserting one refresh cycle at a time. care should be taken to ensure that a sufficient number of refresh cycles are executed. refer to section 4.4.5 for more details. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface dram refresh motorola dsp56004 user? manual 4-35 4.4.5 dram refresh timing table 4-17 shows the typical refresh requirements of some motorola dram devices. note that the column ?eriodic refresh per row?refers to the time between the refresh cycles if refreshing is continuous. to program the refresh timer for periodic refresh requests, the following equation can be used: where: ecd is the refresh divider value, an integer in the range of 1 to 256. prf is the dram periodic refresh period (in seconds) per row (see table 4-17 ). freq is the internal device operating frequency in hz. eps is the prescaler value: 1, 8, or 64. if the refresh cycles are to be executed in a single burst, it is possible to program the refresh timer for the highest refresh request rate possible. table 4-18 shows the timings and bit settings for continuous refresh cycles, cross referenced with appropriate clock frequencies. note: for the continuous method, the drams require a certain time between the refresh of each row. this time does not change for drams of different sizes. table 4-17 typical dram refresh timing requirements device size number of rows whole refresh cycle periodic refresh per row mcm514256a 256 k 4 512 8 ms 15.6 m s mcm51l4256a 256 k 4 512 64 ms 124.8 m s mcm514400 1 m 4 1024 16 ms 15.6 m s mcm51l4400 1 m 4 1024 128 ms 124.8 m s mcm84000 4 m 8 1024 16 ms 15.6 m s mcm8l4000 4 m 8 1024 128 ms 124.8 m s ecd prf freq eps --------------------------------- - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-36 dsp56004 user? manual motorola external memory interface dram refresh table 4-19 shows the timings and bit settings for burst refresh cycles, cross- referenced to appropriate clock frequencies. note: the drams are usually required to refresh all rows within a certain time. this time does not change for drams of different sizes. table 4-18 continuous refresh: timings and settings for eps[1:0] and ecd[7:0] dsp clock frequency max time between refresh cycles eps setting ecd setting actual time between refresh cycles 40 mhz 15.6 m s 124.8 m s 01 00 77 77 15.6 m s 124.8 m s 50 mhz 15.6 m s 124.8 m s 01 00 96 96 15.52 m s 124.2 m s 66 mhz 15.6 m s 124.8 m s 01 00 127 127 15.52 m s 124.2 m s 81 mhz 15.6 m s 124.8 m s 01 00 157 157 15.6 m s 124.8 m s note: timer resolution is for a prescaling of 8. the refresh timer initiates a refresh request every (ecd set + 1) prescale. table 4-19 burst refresh: timings and settings for eps[1:0] and ecd[7:0] dsp clock frequency fast timing mode/ slow timing mode (1 refresh cycle) max time to refresh 512 rows eps setting ecd setting % of execution code time eref is set (fast/slow) 40 mhz 0.225 m s 0.325 m s 8 ms 64 ms 10 10 8 12 1.44% / 2.08% 0.18% / 0.26% 50 mhz 0.180 m s 0.260 m s 8 ms 64 ms 10 10 8 12 1.15% / 1.66% 0.14% / 0.21% 66 mhz 0.136 m s 0.197 m s 8 ms 64 ms 10 10 8 12 0.87% / 1.26% 0.11% / 0.16% 81 mhz n.a. 0.161 m s 8 ms 64 ms n.a. 10 n.a. 12 n.a. / 1.03% n.a. / 0.13% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface dram refresh motorola dsp56004 user? manual 4-37 figure 4-6 shows the timing for a dram refresh cycle when fast timing is selected. figure 4-7 shows the timing for a dram refresh cycle when slow timing is selected. note: timer resolution is for a prescaling of 8. the refresh timer initiates a refresh request every (ecd set + 1) prescale. figure 4-6 timing diagram of a dram refresh cycle (fast) figure 4-7 timing diagram of a dram refresh cycle (slow) clk mras mcas during a refresh cycle: mcs x , mrd and mwr are deasserted (high), data lines remain high impedance, and address lines remain unchanged. 23456789 1 1 aa0298k 2 clk mras mcas during a refresh cycle: mcs x , mrd and mwr are deasserted (high), data lines remain high impedance, and address lines remain unchanged. 23456789101112 13 1 1 aa0299 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-38 dsp56004 user? manual motorola external memory interface emi operating considerations 4.5 emi operating considerations this section describes aspects of emi operation that should be particularly noted by designers of applications using the emi. 4.5.1 emi triggering and pipelining the emi is double-buffered in both the address and the data paths. this feature allows for pipelined operation of consecutive read or write accesses. thus, while a memory access is being performed, the next access can be triggered, proceed through to the address calculation stage where it is kept on hold until the current access is completed. as a result, the emi performance is increased since the address calculation overlaps with actual memory access, and while the dsp side is interrupted for service, the next access is being executed on the memory side. the emi accepts three types of triggering: dram refresh, write transfer, and read transfer. the emi always completes its current operation before checking for pending triggers. the dram refresh has the highest priority. write and read transfers have the same priority and are serviced according to the arrival order. when the emi is idle, two consecutive operations can be triggered without the need to check status bits for any combination of read and write triggers. as long as a trigger is pending, any additional trigger will override and replace the pending one. for better reference to the dsp core activity, emi data accesses can be measured in instruction cycles (i cyc ) where one i cyc equals two processor clock cycles. emi data access durations are denoted by ??i cyc . n can easily be obtained from table 4-10 on page 4-19 and table 4-11 on page 4-20 by dividing the number of clock cycles by 2. for cases where the number of clock cycles is odd, n can be rounded up (conservative approach), or for consecutive emi accesses n can be rounded alternately up and down. the emi pipeline mechanism operates according to the following rules: if both read and write data paths are free (ebsy = 0 and ebdf = 0), and a trigger is generated, it is considered as the first trigger. when this occurs: ebsy is set immediately, the address calculation is executed at the next i cyc , and the external access starts at the next cycle after i cyc and ends n i cyc later. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi operating considerations motorola dsp56004 user? manual 4-39 if an access is being processed (ebsy = 1), an additional trigger can be generated. this trigger will be considered pending if: the address calculation is executed overlapping the last i cyc of the current access, and/or the external access immediately follows, thus providing full bus bandwidth. ebar is incremented and updated (if einr = 1 for read, or einw = 1 for write) one i cyc after the address calculation time frame. following a read access, the data is available on edrr, and can be read by the dsp core: sram modes ?t the first i cyc after completing the external access fast dram mode ?t the last i cyc of the external access slow dram mode ?t the i cyc after the last i cyc of the external access special consideration should be given when triggering a new access after two read accesses since the emi data register buffer (edrb) can be full if the emi data read register (edrr) is also full. in this case the new trigger will remain pending and the new access will not take place until the edrb is empty. the status of the edrb can be verified by checking the ecsr ebdf flag. if ebdf = 0 after a read operation, the edrb is empty and it is possible to start a new access immediately. figure 4-8 illustrates the emi pipeline. figure 4-8 emi pipeline i ? i 0 i 1 i 2 i 3 in? in in+1 in+2 in+3 ebar trig2 edrr trig3 comp1 incr1 comp2 incr2 data access # 1 data access # 2 trig1 i cyc flow core operation emi operation ebsy external access aa0300k read read f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-40 dsp56004 user? manual motorola external memory interface emi operating considerations the following assumptions apply to figure 4-8 : first trigger is generated at i ? (trig1) the address computation of trig1 is done at i 0 . the external access of trig1 begins at i 1 . its duration is n i cyc . the optional increment and update of ebar due to trig1 is done at i 1 . updated ebar of trig1 can be read from the core starting from i 2 . next trigger (trig2) can be driven starting from i 0 . the address computation of trig2 is done at i n . the optional increment and update of ebar due to trig2 is done at i n + 1 . if access #1 is a read access, the data can be read at the dsp core at: ? n + 1 for sram ? n for fast dram mode ? n ?1 for slow dram mode 4.5.2 read data transfer when erts = 0, read accesses are triggered by writing an offset to the eor. when erts = 1, read accesses are triggered by reading the edrr. the word address for a read access is generated by subtracting the offset (stored in the eor) from the base address (stored in one of the ebarx). after obtaining the word address, it is transformed into one or more physical addresses for the actual read accesses. a data word read can require one, two, three, four, or six memory accesses, as specified by the bits ewl[1:0] and ebw. the nibbles or bytes read are held in the edrb until the whole word is formed. after completing the required number of memory accesses, the data word formed in the edrb is transferred to the edrr, setting the edrf status bit, if edrr is empty. optionally, the read interrupt can be generated if read interrupts are enabled. if another data-word-read transfer is pending and the edrb is empty, the emi controller executes the new memory transfer. if the dsp has read the data from the edrr (clearing edrf), the contents of the edrb (if full) is transferred to the edrr again, setting the edrf status bit. if no other read request is pending, memory accesses cease. the emi read interrupt can also be generated when both the edrb and the edrr are full. in this case, a single fast interrupt service with two movep instructions can read two data words. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi operating considerations motorola dsp56004 user? manual 4-41 the memory read transfer starts only if the edrb is empty. data formed in the edrb is transferred to the edrr only if the edrr is empty. this feature ensures synchronization between dsp reads of data and memory reads, even if the dsp is not emptying the edrr in real time, as can happen while debugging via the once port. the ebarx can optionally be post-incremented by one after each read transfer. in this case, the incremented value will be available in the ebarx at the end of the first executed instruction after all memory read accesses have occurred for this particular memory-read transfer. example 4-2 successive memory-read transfers with erts = 0 the following procedure describes a sequence of successive memory-read transfers with erts = 0. this procedure utilizes the pipeline property for better performance. movep #ram,x:< 4-46 dsp56004 user? manual motorola external memory interface data-delay structure 4.6 data-delay structure delayed data structures, commonly used in audio dsp algorithms, can be implemented by means of data-delay buffers in memory. a data-delay buffer is a bank of memory in which data samples are stored in a sequential manner and where a relationship exists between time delay and memory location. the longest delay for a given data sequence corresponds to the length of the data-delay buffer (the size of the memory bank). data-delay buffers of any length, within the available memory range, are supported by the emi. a memory buffer for delayed data is defined in terms of a base address and a collection of offset values (the taps). data-delay buffers are implemented in the emi by means of ?indows?that move over all the memory address range. the base address points to the latest stored (newest) data sample, and offset values are subtracted from the base address to generate addresses that point to delayed data samples. the amount of the delay is defined by the offset value. normally, the base address of each data-delay buffer is incremented every time a new data sample is stored and this causes the window to move one position ahead in the range of physical memory addresses. the data-delay structure is illustrated in figure 4-9 . figure 4-9 illustration of the data-delay structure base address (points to latest data sample). points to delayed data sample. offset value illustration of two independent data-delay buffers of different lengths illustration of one data-delay buffer ascending progression over the entire memory address space. buffer 1 pointer buffer 0 pointer region of valid delayed data moving along the memory address range (ebar) (ebar) aa0401 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface data-delay structure motorola dsp56004 user? manual 4-47 the emi architecture is capable of managing several concurrent data-delay processes. each data-delay buffer is defined by its own base address. multiple data-delay buffers can be implemented by saving and restoring the contents of the ebarx as required. the maximum delay required in a data sequence implicitly determines the data-delay buffer length. two restrictions must be considered: the programmer must define non-overlapping initial memory regions for the data-delay buffers within the available memory address range. the data-delay buffers must be updated at the same speed; that is, new data samples are stored at the same rate in all buffers. this ensures that no data-delay buffer will overwrite the data of another buffer. normally, the dsp programmer determines the base address values arbitrarily such that non-overlapped buffers are guaranteed. this is done in the initialization stage only. afterwards, the programmer need not be concerned with the base address value. to summarize, the data-delay buffer is normally handled, in the steady state (after initialization and buffer-filling stage), as follows: upon receiving a new data sample, the data sample is temporarily saved in an internal memory location. it might be used in many audio algorithms as the most recent data sample. any number of random-delayed samples are read from the specific buffer in the external memory by requesting read operations with different offset values while ebarx is loaded with the base address for the specific data buffer. this is operation is accomplished by writing the desired offset values to the eor, triggering the read operation. the contents of ebarx should be kept constant during the read operations; that is, keep einr = 0 in the ecsr. the most recent data sample (temporarily held in an internal memory location) is stored to the specified data buffer in the external memory by writing the data word to the data write register when einw (in the ecsr) is set. in this way the new sample is stored in the external memory data buffer while ebarx is incremented, preparing the base address for the next sample. the contents of ebarx should now be saved to an internal memory location to be used in future accesses to this data-delay buffer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-48 dsp56004 user? manual motorola external memory interface emi-to-memory connection 4.7 emi-to-memory connection the emi can be easily interfaced directly to both sram and dram devices via its external pins. no interface logic is required. usually the hardware designer will connect dram or sram to the emi to implement data buffers that will be accessed using the relative addressing modes. it is possible to concurrently connect an additional static memory device if one of the gpio pins or another external source is used as device select for the device and if the device is accessed using the absolute addressing mode. the absolute addressing mode is useful for program bootstrap or overlays. figure 4-10 shows how to connect two 256 k 4 dram devices for the data buffers and an sram for program bootstrap or overlays. figure 4-10 dram for data delay buffers and for sram for bootstrap a[8:0] dq[3:0] dram mcm514256a w g ras cas sram (mcm60256a) ma[14:0] md[7:0] a[14:0] dq[7:0] e w g gpio3 dram relative addressing absolute addressing mwr mrd mras mcas dsp (emi) aa0260k a[8:0] dq[3:0] dram mcm514256a w g ras cas f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi-to-memory connection motorola dsp56004 user? manual 4-49 figure 4-11 shows how to connect four 32 k 8 sram devices for the data buffers and an sram for program bootstrap or overlays. for applications requiring sram devices for implementation of the data-delay buffers (e.g., for noise considerations) and requiring addressing of more than 256 k 8 physical locations, it is possible to use the dram addressing modes with a large array of sram devices. an external latch must be used to demultiplex the row and column addresses and in this way to obtain the sram address. figure 4-11 sram for data delay buffers and for bootstrap ma[14:0] md[7:0] a[14:0] dq[7:0] sram mcm60256a e w g gpio3 sram relative addressing absolute addressing mwr mrd mcs0 mcs1 mcs2 mcs3 dsp (emi) aa0261k a[14:0] dq[7:0] sram mdm6206 w g e a[14:0] dq[7:0] sram mdm6206 w g e a[14:0] dq7:0 sram mdm6206 w g e a[14:0] dq[7:0] sram mcm6206 w g e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-50 dsp56004 user? manual motorola external memory interface emi timing figure 4-12 shows how to connect a 512 k 8 sram to the emi. 4.8 emi timing table 4-20 shows the maximum dsp clock frequencies while using typical dram devices: figure 4-12 replacing drams with srams for large arrays table 4-20 maximum dsp clock frequencies when using dram dram max freq edtm mcm54400a?0 ns 66 mhz 81 mhz 0 1 mcm54400a?0 ns 50 mhz 81 mhz 0 1 ma[14:0] md[7:0] d[9:0] clk a[18:0] dq[7:0] idtmp4008s w g cs dram relative addressing mras mrd mcas d?f idt74fct821a mwr ma[9:0] q[9:0] dsp (emi) aa0262k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi timing motorola dsp56004 user? manual 4-51 table 4-21 shows the maximum dsp clock frequencies while using typical sram devices): table 4-22 shows the maximum dsp clock frequencies while using typical eproms using the absolute addressing sram mode devices: 4.8.1 timing diagrams for dram addressing modes when operating in the dram modes, the timing is defined by the ecsr edtm bit. the timing is classified as fast (edtm = 0) or slow (edtm = 1). table 4-21 maximum dsp clock frequencies when using sram sram max freq estm[3:0] mcm6226?5 ns 81 mhz 0000 mcm6206?5 ns 66 mhz 0000 table 4-22 maximum dsp clock frequencies when using eprom eprom max freq estm[3:0] ws57c256?5 ns 66 mhz 0000 ws57c256?0 ns 50 mhz 0000 ws57c256?0 ns 50 mhz 0001 ws57c256?20 ns 46 mhz 0010 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-52 dsp56004 user? manual motorola external memory interface emi timing 4.8.1.1 fast timing mode figure 4-13 shows the absolute addressing mode timing for an 8-bit word/8-bit bus memory access or physical memory access. the numbers in the table are memory-access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left-justified such that the 8-bit word is read from and written into the upper-most byte of the 24-bit word (bits 23?6). figure 4-13 fast read or write dram access timing? 8-bit word/8-bit bus?elative addressing, or each physical access in the absolute addressing modes set up row address 1 2 3 r/w bits 23?6 4 5 6 finish last r/w cycle 7 8 start new memory cycle 12 column address row address clk address mras mcas mwr mrd row address data out valid data mwr mrd read write valid data data in aa0403 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi timing motorola dsp56004 user? manual 4-53 figure 4-14 shows the timing using relative addressing mode for a 16-bit word/8-bit bus memory access or an 8-bit word/4-bit bus memory access. the numbers in the table are memory access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left-justified such that the 16-bit word is read from and written into the upper-most two bytes of the 24-bit word (bits 23?). data is transferred one byte at a time for 16-bit words or four bits at time for 8-bit words. figure 4-14 fast read or write dram access timing? 16-bit word/8-bit bus, or 8-bit word/4-bit bus?elative addressing set up row address 1 2 3 r/w bits 23?6; 23?0 4 5 6 r/w bits 15?; 19?6 7 8 9 finish last r/w cycle 10 11 new memory cycle 1 2 last column address column address row address clk address mras mcas mwr mrd row address data out valid data valid data mwr mrd read write valid data valid data data in aa0404 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-54 dsp56004 user? manual motorola external memory interface emi timing figure 4-15 shows the timing using relative addressing mode for a 16-bit word/4-bit bus memory access. the numbers in the table are memory-access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left-justified such that the 16-bit word is read from and written into the upper-most two bytes of the 24-bit word (bits 23?). figure 4-15 fast read or write dram access timing? 16-bit word/4-bit bus?elative addressing set up row address 1 2 3 r/w bits 23?6 4 5 6 r/w bits 19?6 7 8 9 r/w bits 15?2 10 11 12 r/w bits 11? 13 14 15 finish last r/w cycle 16 17 new memory cycle 1 2 last column address column address row address clk address mras mcas mwr mrd row address data out valid data valid data mwr mrd read write valid data valid data data in aa0405 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi timing motorola dsp56004 user? manual 4-55 figure 4-16 shows the timing using relative addressing mode for a 20-bit word/8-bit bus memory access, 24-bit word/8-bit bus memory access, or 12-bit word/4-bit bus memory access. the numbers in the table are memory-access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left-justified such that the 20-bit, 24-bit, or 12-bit word is read from and written into the upper-most 20, 24, or 12 bits of the 24-bit word. data is transferred one byte at a time for 16- and 20-bit words or four bits at time for 12-bit words. figure 4-16 fast read or write dram access timing? 20-bit or 24-bit word/8-bit bus, or 12-bit word/4-bit bus?elative addressing set up row address 1 2 3 r/w bits 23?6 4 5 6 r/w bits 15? 7 8 9 r/w bits 7?/0 10 11 12 finish last r/w cycle 13 14 new memory cycle 1 2 last column address column address row address clk address mras mcas mwr mrd row address data out valid data valid data mwr mrd read write valid data valid data data in aa0406 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-56 dsp56004 user? manual motorola external memory interface emi timing figure 4-17 shows the timing using relative addressing mode for a 20-bit word/4-bit bus memory access. the numbers in the table are memory-access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left-justified such that the 20-bit word is read from and written into the upper-most portion of the 24-bit word (bits 23?). figure 4-17 fast read or write dram access timing? 20-bit word/4-bit bus?elative addressing set up row address 1 2 3 r/w bits 23?0 4 5 6 r/w bits 19?6 7 8 9 r/w bits 15?2 10 11 12 r/w bits 11? 13 14 15 r/w bits 7? 16 17 18 finish last r/w cycle 19 20 new memory cycle 1 2 last column address column address row address clk address mras mcas mwr mrd row address data out valid data valid data mwr mrd read write valid data valid data data in aa0407 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi timing motorola dsp56004 user? manual 4-57 figure 4-18 shows the timing using relative addressing mode for a 24-bit word/4-bit bus memory access. the numbers in the table are memory-access clock cycles and correspond to clock cycles of the timing figure directly below. figure 4-18 fast read or write dram access timing? 24-bit word/4-bit bus?elative addressing set up row address 1 2 3 r/w bits 23?0 4 5 6 r/w bits 19?6 7 8 9 r/w bits 15?2 10 11 12 r/w bits 11? 13 14 15 r/w bits 7? 16 17 18 r/w bits 3? 19 20 21 finish last r/w cycle 22 23 new memory cycle 1 2 last column address column address row address clk address mras mcas mwr mrd row address data out valid data valid data mwr mrd read write valid data valid data data in aa0408 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-58 dsp56004 user? manual motorola external memory interface emi timing 4.8.1.2 slow timing mode figure 4-19 shows the absolute addressing mode timing for an 8-bit word/8-bit bus memory access or physical memory access. the numbers in the table are memory-access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left-justified such that the 8-bit word is read from and written into the upper-most byte of the 24-bit word (bits 23?6). figure 4-19 slow read or write dram access timing? column address row address valid data clk address mras mcas mwr mrd data in row address data out valid data mwr mrd read write 8-bit word/8-bit bus?elative addressing, or each physical access in the absolute addressing modes set up row address 1234 r/w bits 23?6 5678 finish last r/w cycle 9 10 11 12 new memory cycle 1 2 aa0409 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi timing motorola dsp56004 user? manual 4-59 figure 4-20 shows the timing using relative addressing mode for a 16-bit word/8-bit bus memory access or 8-bit word/4-bit bus memory access. the numbers in the table are memory access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left justified such that the 16-bit word is read from and written into the upper-most two bytes of the 24-bit word (bits 23?). data is transferred one byte at a time for 16-bit words or four bits at time for 8-bit words. figure 4-20 slow read or write dram access timing? last column address column address row address valid data valid data clk address mras mcas mwr mrd data in row address data out valid data valid data mwr mrd read write 16-bit word/8-bit bus, or 8 bit word/4-bit bus?elative addressing set up row address 1234 r/w bits 23?6; 23?0 5678 r/w bits 15?; 19?6 9 10 11 12 finish last r/w cycle 13 14 15 16 new memory cycle 1 2 aa0410 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-60 dsp56004 user? manual motorola external memory interface emi timing figure 4-21 shows the timing using relative addressing mode for a 16-bit word/4-bit bus memory access. the numbers in the table are memory access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left justified such that the 16-bit word is read from and written into the upper-most two bytes of the 24-bit word (bits 23?). figure 4-21 slow read or write dram access timing? last column address column address row address valid data valid data clk address mras mcas mwr mrd data in row address data out valid data valid data mwr mrd read write 16-bit word/4-bit bus?elative addressing set up row address 1234 r/w bits 23?0 5678 r/w bits 19?6 9 10 11 12 r/w bits 15?2 13 14 15 16 r/w bits 11? 17 18 19 20 finish last r/w cycle 21 22 23 24 new memory cycle 1 2 aa0411 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi timing motorola dsp56004 user? manual 4-61 figure 4-22 shows the timing using relative addressing mode for an 20-bit word/8-bit bus memory access, 24-bit word/8-bit bus memory access, or 12-bit word/4-bit bus memory access. the numbers in the table are memory access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left justified such that the 20-bit, 24-bit, or 12-bit word is read from and written into the upper-most 20-bits, 24-bits, or 12-bits of the 24-bit word. data is transferred one byte at a time for 16-bit and 12-bit words or four bits at time for 12-bit words. figure 4-22 slow read or write dram access timing? last column address column address row address valid data valid data clk address mras mcas mwr mrd data in row address data out valid data valid data mwr mrd read write 20-bit or 24-bit word/8-bit bus, or 12-bit word/4-bit bus?elative addressing set up row address 1234 r/w bits 23?6; 23?0 5678 r/w bits 15?; 19?6 9 10 11 12 r/w bits 7?/0; 15?2 13 14 15 16 finish last r/w cycle 17 18 19 20 new memory cycle 1 2 aa0412 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-62 dsp56004 user? manual motorola external memory interface emi timing figure 4-23 shows the timing using relative addressing mode for a 20-bit word/4-bit bus memory access. the numbers in the table are memory access clock cycles and correspond to clock cycles of the timing figure directly below. data accesses are left justified such that the 20-bit word is read from and written into the upper-most portion of the 24-bit word (bits 23?). figure 4-23 slow read or write dram access timing? last column address column address row address valid data valid data clk address mras mcas mwr mrd data in row address data out valid data valid data mwr mrd read write 20-bit word/4-bit bus?elative addressing set up row address 1234 r/w bits 23?0 5678 r/w bits 19?6 9 10 11 12 r/w bits 15?2 13 14 15 16 r/w bits 11? 17 18 19 20 r/w bits 7? 21 22 23 24 finish last r/w cycle 25 26 27 28 new memory cycle 1 2 aa0413 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external memory interface emi timing motorola dsp56004 user? manual 4-63 figure 4-24 shows the timing using relative addressing mode for a 24-bit word/4-bit bus memory access. the numbers in the table are memory access clock cycles and correspond to clock cycles of the timing figure directly below. figure 4-24 slow read or write dram access timing? last column address column address row address valid data valid data clk address mras mcas mwr mrd data in row address data out valid data valid data mwr mrd read write 24-bit word/4-bit bus?elative addressing set up row address 1234 r/w bits 23?0 5678 r/w bits 19?6 9 10 11 12 r/w bits 15?2 13 14 15 16 r/w bits 11? 17 18 19 20 r/w bits 7? 21 22 23 24 r/w bits 3? 25 26 27 28 finish last r/w cycle 29 30 31 32 new memory cycle 1 2 aa0414 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-64 dsp56004 user? manual motorola external memory interface emi timing 4.8.2 timing diagrams for sram addressing modes when operating in the sram modes, the timing is selected by the estm bits in the ecsr (see section 4.2.7 on page 4-10). figure 4-25 shows the timing diagrams for read and write operations to/from sram memory. the cycle timing is shown at the top; there are two clock cycles to set up the transfer and then from 1 to 16 cycles (as determined by the estm bits), followed by the last cycle. this completes one memory access. there can be from one to six memory accesses needed to transfer one word, as shown in table 4-11 on page 4-20. figure 4-25 sram read/write timing valid data clk address mcs mcas mwr mrd data in 12 repeat 1 mras valid data mwr mrd data out read write one nibble or byte access aa0415 last estm + 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual 5-1 section 5 serial host interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-2 dsp56004 user? manual motorola serial host interface 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 serial host interface internal architecture . 5-4 5.3 serial host interface programming model. . . . 5-4 5.4 characteristics of the spi bus . . . . . . . . . . . . . . . 5-19 5.5 characteristics of the i2c bus . . . . . . . . . . . . . . . 5-19 5.6 shi programming considerations . . . . . . . . . . . . 5-22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface introduction motorola dsp56004 user? manual 5-3 5.1 introduction the serial host interface (shi) is a serial i/o interface that provides a path for communication and program/coefficient data transfers between the dsp and an external host processor. the shi is capable of communicating with other serial peripheral devices as well. the shi may be configured to interface directly to either of two well-known and widely used synchronous serial buses: the serial peripheral interface (spi) bus defined by motorola and the inter integrated-circuit control (i 2 c) bus defined by philips. the shi handles both spi and i 2 c bus protocols, as required, from a slave or a single-master device. in order to minimize dsp overhead, the shi supports single-, double-, and triple-byte data transfers. the shi has a ten-word receive first-in, first-out (fifo) register that permits receiving up to thirty bytes before generating a receive interrupt. this reduces the dsp overhead for data reception. when configured in the spi mode, the shi is able to: identify its slave selection (in slave mode) simultaneously transmit data (shift out serially) and receive data (shift in serially) directly operate with words 8, 16, and 24 bits long generate vectored interrupts, separately for receive and transmit events, and update status bits generate a separate vectored interrupt in the event of a receive exception generate a separate vectored interrupt in the event of a bus-error exception generate the serial clock signal (in master mode) when configured in the i 2 c mode, the shi is able to: detect/generate start and stop events identify its slave (id) address (in slave mode) identify the transfer direction (receive/transmit) transfer data byte-wise according to the scl clock line generate an ack signal following a byte receive inspect an ack signal following a byte transmit directly operate with words 8, 16, and 24 bits long f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-4 dsp56004 user? manual motorola serial host interface serial host interface internal architecture generate vectored interrupts separately for receive and transmit events and update status bits generate a separate vectored interrupt if a receive exception occurs generate a separate vectored interrupt if a bus error exception occurs generate the clock signal (in master mode) 5.2 serial host interface internal architecture the dsp views the shi as a memory-mapped peripheral in the x data memory space. the dsp may use the shi as a normal memory-mapped peripheral using standard polling or interrupt programming techniques. memory mapping allows dsp communication with the shi registers to be accomplished using standard instructions and addressing modes. in addition, the movep instruction allows interface-to-memory and memory-to-interface data transfers without going through an intermediate register. the single master configuration allows the dsp to directly connect to dumb peripheral devices. for that purpose, a programmable baud-rate generator is included to generate the clock signal for serial transfers. the host side invokes the shi, for communication and data transfer with the dsp, through a shift register that may be accessed serially using either the i 2 c or the spi bus protocols. figure 5-1 shows the shi block diagram. the shi clock generator generates the serial clock to the shi if the interface operates in the master mode. the clock generator is disabled if the interface operates in the slave mode. when the shi operates in the slave mode, the clock is external and is input to the shi. figure 5-2 illustrates the internal clock path connections. it is the user? responsibility to select the proper clock rate within the range as defined in the i 2 c and spi bus specifications. 5.3 serial host interface programming model the serial host interface programming model is divided in two parts: the host side and the dsp side. the registers that are available to the programmer on the host side are shown in figure 5-3 on page 5-6, and the registers that are available to the programmer on the dsp side are shown in figure 5-4 on page 5-7. these registers are described in the following paragraphs. the interrupt vector table for the serial host interface is shown in table 5-1 , and the exceptions generated by the shi are prioritized as shown in table 5-2 on page 5-6. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface serial host interface programming model motorola dsp56004 user? manual 5-5 figure 5-1 serial host interface block diagram figure 5-2 shi clock generator dsp global data bus dsp accessible host accessible sck/scl miso/sda mosi/ha0 ss /ha2 hrx (fifo) hreq hcsr htx hckr 24 bit hsar clock generator controller logic slave address recognition unit (sar) pin control logic input/output shift register (iosr) aa0416k shi hmst hmst = 0 hmst = 1 sck/scl divide by 1 or 8 divide by 1 to divide by 64 hrs hdm0-hdm5 shi clock f osc divide by 2 controller clock logic cpha,cpol,hi 2 c aa0417k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-6 dsp56004 user? manual motorola serial host interface serial host interface programming model table 5-1 shi interrupt vectors address interrupt source p: $0020 shi transmit data p: $0022 shi transmit underrun error p: $0024 shi receive fifo not empty p: $0026 reserved p: $0028 shi receive fifo full p: $002a shi receive overrun error p: $002c shi bus error table 5-2 shi internal exception priorities priority exception highest shi bus error shi receive overrun error shi transmit underrun error shi receive fifo full shi transmit data lowest shi receive fifo not empty figure 5-3 shi programming model?ost side 0 i/o shift register (iosr) iosr 23 aa0418 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface serial host interface programming model motorola dsp56004 user? manual 5-7 5.3.1 shi input/output shift register (iosr)?ost side the variable length input/output shift register (iosr) can be viewed as a serial-to-parallel and parallel-to-serial buffer in the shi. the iosr is involved with every data transfer in both directions (read and write). data is shifted in and out most significant bit (msb) first in compliance with the i 2 c and spi bus protocols. the iosr cannot be accessed directly either by the host processor or by the dsp. it is fully controlled by the shi controller logic. in single-byte data transfer modes, the highest byte of the iosr is activated as a shift register. in 16-bit data transfer modes, the two higher bytes of the iosr are activated as the shift register. in 24-bit transfer modes, all three bytes of the iosr comprise the shift register (see figure 5-5 ). figure 5-4 shi programming model?sp side 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 23 shi receive data fifo (hrx) (read only, x: $fff3) hrx shi transmit data register (htx) (write only, x: $fff3) reserved bit, read as 0, should be written with 0 for future compatibility. hdm5 hfm1 0 7654321 hfm0 hdm2 hdm0 hdm1 hrs hdm3 hdm4 cpha cpol shi clock control register (hckr) x: $fff0 0 23 htx 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 hen 0 7654321 hm1 hi2c hm0 hrqe0 hmst hrne hber hrff hroe hbusy hrqe1 hidle shi control/status register (hcsr) hrie0 hrie1 htue htde htie x: $fff1 fifo (10 words deep) hbie hfifo 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 ha6 0 7654321 ha3 ha4 ha5 shi i 2 c slave address register (hsar) x: $fff2 ha1 aa0419 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-8 dsp56004 user? manual motorola serial host interface serial host interface programming model 5.3.2 shi host transmit data register (htx)?sp side the host transmit data register (htx) is used for dsp-to-host data transfers. the htx register is 24 bits wide. writing to the htx register clears the htde flag. the dsp may program the htie bit to cause a host transmit data interrupt when htde is set (see 5.3.6.10 hcsr transmit-interrupt enable (htie)?it 11 on page 5-16). data should not be written to the htx until htde is set in order to prevent overwriting the previous data. htx is reset to the empty state when in stop mode and during hardware reset, software reset, and individual reset. in the single-byte data transfer mode the most significant byte of the htx is transmitted; in the double-byte mode the two most significant bytes, and in the triple-byte mode all the htx is transferred. 5.3.3 shi host receive data fifo (hrx)?sp side the 24-bit host receive data fifo (hrx) is a ten-word-deep, first-in, first-out (fifo) register used for host-to-dsp data transfers. the serial data is received via the shift register and then loaded into the hrx. in the single-byte data transfer mode, the most significant byte of the shift register is transferred to the hrx (the other bits are filled with 0s); in the double-byte mode the two most significant bytes (the least significant byte is filled with 0s) are transferred, and in the triple-byte mode, all 24 bits are transferred to the hrx. the hrx may be read by the dsp while the fifo is being loaded from the shift register. the hrx is reset to the empty state (cleared) when the chip is in stop mode, and during hardware reset, software reset, and individual reset. figure 5-5 shi i/o shift register (iosr) 16 23 8 15 0 7 8 bit data mode 16 bit data mode 24 bit data mode mode of operation stops data when data mode is selected passes data when data mode is selected aa0420k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface serial host interface programming model motorola dsp56004 user? manual 5-9 5.3.4 shi slave address register (hsar)?sp side the 24-bit slave address register (hsar) is used when the shi operates in the i 2 c slave mode and is ignored in the other operational modes. hsar holds five bits of the 7-bit slave address of the device. the shi also acknowledges the general call address (all 0s, 7-bit address, and a 0 r/w bit) specified by the i 2 c protocol. hsar cannot be accessed by the host processor. 5.3.4.1 hsar reserved bits?its 17?,19 these bits are reserved and unused. they read as 0 and should be written with 0 for future compatibility. 5.3.4.2 hsar i 2 c slave address (ha[6:3], ha1)?its 23?0,18 part of the i 2 c slave address is stored in the read/write ha[6:3], ha1 bits of hsar. the full 7-bit slave address is formed by combining the ha[6:3], ha1 bits with the ha0 and ha2 pins to obtain the ha[6:0] slave address. the full 7-bit slave address is compared to the received address byte whenever an i 2 c master device initiates an i 2 c bus transfer. during hardware reset or software reset, the ha[6:3] bits are set to 1011 while ha1 is cleared; this results in a default slave address of 1011_ha2_0_ha0. 5.3.5 shi clock control register (hckr)?sp side the shi clock control register (hckr) is a 24-bit read/write register that controls the shi clock generator operation. the hckr bits are cleared during hardware reset or software reset, except for cpha, which is set. the hckr bits should be modified only while the shi is in the individual reset state (hen = 0 in the hcsr). the hckr is not affected by the stop state. note that the maximum-allowed internally generated bit clock frequency is f osc / 4 for the spi mode and f osc / 6 for the i 2 c mode (the maximum-allowed externally generated bit clock frequency is f osc / 3 for the spi mode and f osc / 5 for the i 2 c mode). the programmer should not use the combination hrs = 1 and hdm[5:0] = 000000, since it may cause synchronization problems and improper operation (it is therefore considered an illegal combination). the hckr bits are described in the following paragraphs. 5.3.5.1 clock phase and polarity (cpha and cpol)?its 1? the programmer may select any of four combinations of serial clock (sck) phase and polarity when operating in the spi mode (refer to figure 5-6 on page 5-11). the clock polarity is determined by the clock polarity (cpol) control bit, which selects an active-high or active-low clock. when cpol is cleared, it produces a steady-state low value at the sck pin of the master device whenever data is not being transferred. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-10 dsp56004 user? manual motorola serial host interface serial host interface programming model if the cpol bit is set, a high value is produced at the sck pin of the master device whenever data is not being transferred. the clock phase (cpha) bit controls the relationship between the data on the miso and mosi pins and the clock produced or received at the sck pin. this control bit is used in conjunction with the cpol bit to select the desired clock-to-data relationship. the cpha bit, in general, selects the clock edge that captures data and allows it to change states. it has its greatest impact on the first bit transmitted (msb) in that it does or does not allow a clock transition before the data capture edge. when in slave mode and cpha = 0, the ss line must be deasserted and asserted by the external master between each successive word transfer. ss must remain asserted between successive bytes within a word. the dsp core should write the next data word to htx when htde = 1, clearing htde. however, the data will be transferred to the shift register for transmission only when ss is deasserted. htde is set when the data is transferred from htx to the shift register. when in slave mode and cpha = 1, the ss line may remain asserted between successive word transfers. the ss must remain asserted between successive bytes within a word. the dsp core should write the next data word to htx when htde = 1, clearing htde. the htx data will be transferred to the shift register for transmission as soon as the shift register is empty. htde is set when the data is transferred from htx to the shift register. when in master mode and cpha = 0, the dsp core should write the next data word to htx when htde = 1, clearing htde; the data is transferred immediately to the shift register for transmission. htde is set only at the end of the data word transmission. note that the master is responsible for deasserting and asserting the slave ss line between word transmissions. when in master mode and cpha = 1, the dsp core should write the next data word to htx when htde = 1, clearing htde. the htx data will be transferred to the shift register for transmission as soon as the shift register is empty. htde is set when the data is transferred from htx to the shift register. the clock phase and polarity should be identical for both the master and slave spi devices. cpha and cpol are functional only when the shi operates in the spi mode, and are ignored in the i 2 c mode. the cpha bit is set and the cpol bit is cleared during hardware reset and software reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface serial host interface programming model motorola dsp56004 user? manual 5-11 5.3.5.2 hckr prescaler rate select (hrs)?it 2 the hrs bit controls a prescaler in series with the clock generator divider. this bit is used to extend the range of the divider when slower clock rates are desired. when hrs is set, the prescaler is bypassed. when hrs is cleared, the fixed divide-by-eight prescaler is operational. hrs is ignored when the shi operates in the slave mode. the hrs bit is cleared during hardware reset and software reset. 5.3.5.3 hckr divider modulus select (hdm[5:0])?its 8? the hdm[5:0] bits specify the divide ratio of the clock generator divider. a divide ratio between one and sixty-four (hdm[5:0] = 0 to $3f) may be selected. when the shi operates in the slave mode, the hdm[5:0] bits are ignored. the hdm[5:0] bits are cleared during hardware reset and software reset. 5.3.5.4 hckr reserved bits?its 23?4, 11? these bits in hckr are reserved and unused. they are read as 0s and should be written with 0s for future compatibility. 5.3.5.5 hckr filter mode (hfm[1:0]) ?bits 13?2 the read/write control bits hfm[1:0] specify the operational mode of the noise reduction filters as described in table 5-3 . the filters are designed to eliminate undesired spikes that might occur on the clock and data-in lines and allow the shi to operate in noisy environments when required. one filter is located in the input path of the sck/scl line and the other is located in the input path of the data line (i.e., the figure 5-6 spi data-to-clock timing diagram internal strobe for data capture msb654321lsb (cpol = 0, cpha = 0) (cpol = 0, cpha = 1) (cpol = 1, cpha = 0) (cpol = 1, cpha = 1) ss sck sck sck sck miso/ mosi aa0421 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-12 dsp56004 user? manual motorola serial host interface serial host interface programming model sda line when in i 2 c mode, the miso line when in master spi mode, and the mosi line when in slave spi mode). when hfm[1:0] are cleared, the filter is bypassed (spikes are not filtered out). this mode is useful when higher bit-rate transfers are required and the shi operates in a noise-free environment. when hfm1 = 1 and hfm0 = 0, the narrow-spike-tolerance filter mode is selected. in this mode the filters eliminate spikes with durations of up to twenty nanoseconds. this mode is suitable for use in mildly noisy environments and imposes some limitations on the maximum achievable bit-rate transfer. when hfm1 = 1 and hfm0 = 1, the wide-spike-tolerance filter mode is selected. in this mode the filters eliminate spikes up to one-hundred nanoseconds. this mode is recommended for use in noisy environments; the bit-rate transfer is strictly limited. the wide-spike-tolerance filter mode is highly recommended for use in i 2 c bus systems as it fully conforms to the i 2 c bus specification and improves noise immunity. hfm[1:0] are cleared during hardware reset and software reset. after changing the filter bits in the hckr register to a non-bypass mode (hfm[1:0] not equal to ?0? the programmer should wait at least ten times the tolerable spike width before enabling the shi (setting the hen bit in the hcsr register). similarly, after changing the i 2 c bit in the hcsr or the cpol bit in the hckr, while the filter mode bits are in the non-bypass mode (hfm[1:0] not equal to ?0?, the programmer should wait at least ten times the tolerable spike width before enabling the shi (setting hen in the hcsr register). table 5-3 shi noise reduction filter mode hfm1 hfm0 description 0 0 bypassed (disabled) 0 1 reserved 1 0 narrow spike tolerance 1 1 wide spike tolerance f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface serial host interface programming model motorola dsp56004 user? manual 5-13 5.3.6 shi control/status register (hcsr)?sp side the hcsr register is a 24-bit read/write register that controls the serial host interface operation and reflects its status. each bit is described in one of the following paragraphs. when in the stop state or during individual reset, the hcsr status bits are reset to their hardware-reset state, while the control bits are not affected. 5.3.6.1 hcsr host enable (hen)?it 0 the read/write control bit host enable (hen) enables the overall operation of the shi. when hen is set, shi operation is enabled. when hen is cleared, the shi is disabled (individual reset state, see below). the hckr register and the hcsr control bits are not affected when hen is cleared. when operating in master mode, hen should be cleared only after the shi is idle (hbusy = 0). hen is cleared during hardware reset and software reset. note: while the shi is in the individual reset state, shi input pins are inhibited, output and bidirectional pins are disabled (high impedance), the hcsr status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. the individual reset state is entered following a one-instruction-cycle delay after clearing hen. 5.3.6.2 hcsr i 2 c/spi selection (hi 2 c)?it 1 the read/write control bit hi 2 c selects whether the shi operates in the i 2 c or spi modes. when hi 2 c is cleared, the shi operates in the spi mode. when hi 2 c is set, the shi operates in the i 2 c mode. hi 2 c affects the functionality of the shi pins as described in section 2 pin descriptions . it is recommended that an shi individual reset be generated (hen cleared) before changing hi 2 c. hi 2 c is cleared during hardware reset and software reset. 5.3.6.3 hcsr serial host interface mode (hm[1:0])?its 3? the read/write control bits hm[1:0] select the size of the data words to be transferred, as shown in table 5-4 . hm[1:0] should be modified only when the shi is idle (hbusy = 0). hm[1:0] are cleared during hardware reset and software reset. 5.3.6.4 hcsr reserved bits?its 23, 18, 16, and 4 these bits in hcsr are reserved and unused. they are read as 0s and should be written with 0s for future compatibility. table 5-4 shi data size hm1 hmo description 0 0 8-bit data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-14 dsp56004 user? manual motorola serial host interface serial host interface programming model 5.3.6.5 hcsr fifo-enable control (hfifo)?it 5 the read/write control bit hcsr fifo-enable control (hfifo) selects the size of the receive fifo. when hfifo is cleared, the fifo has a single level. when hfifo is set, the fifo has ten levels. it is recommended that an shi individual reset be generated (hen cleared) before changing hfifo. hfifo is cleared during hardware reset and software reset. 5.3.6.6 hcsr master mode (hmst)?it 6 the read/write control bit hcsr master (hmst) determines the operating mode of the shi. if hmst is set, the interface operates in the master mode. if hmst is cleared, the interface operates in the slave mode. the shi supports a single-master configuration, in both i 2 c and spi modes. when configured as an spi master, the shi drives the sck line and controls the direction of the data lines mosi and miso. the ss line must be held deasserted in the spi master mode; if the ss line is asserted when the shi is in spi master mode, a bus error will be generated (the hcsr hber bit will be set; see 5.3.6.17 host bus error (hber)?it 21 ). when configured as an i 2 c master, the shi controls the i 2 c bus by generating start events, clock pulses, and stop events for transmission and reception of serial data. it is recommended that an shi individual reset be generated (hen cleared) before changing hmst. hmst is cleared during hardware reset and software reset. 5.3.6.7 hcsr host request enable (hrqe[1:0])?its 8? the read/write host request enable control bits (hrqe[1:0]) are used to enable the operation of the hreq pin. when hrqe[1:0] are cleared, the hreq pin is disabled and held in the high impedance state. if either hrqe0 or hrqe1 are set and the shi is operating in a master mode, the hreq pin becomes an input that controls the serial clock; deasserting hreq will suspend the serial clock. if either hrqe0 or hrqe1 are set and the shi is operating in a slave mode, hreq becomes an output and its operation is defined as shown in table 5-5 . hrqe[1:0] should be modified only when the shi is idle (hbusy = 0). hrqe[1:0] are cleared during hardware reset and software reset. 0 1 16-bit data 1 0 24-bit data 1 1 reserved table 5-4 shi data size (continued) hm1 hmo description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface serial host interface programming model motorola dsp56004 user? manual 5-15 5.3.6.8 hcsr idle (hidle)?it 9 the read/write control/status bit host idle (hidle) is used only in the i 2 c master mode; it is ignored otherwise. it is only possible to set the hidle bit during writes to the hcsr register. hidle is cleared by writing to htx. to ensure correct transmission of the slave address byte, hidle should be set only when the htx is empty (htde = 1). after hidle is set, a write to the htx will clear hidle and cause the generation of a stop event, a start event, and then the transmission of the eight msbs of the data as the slave address byte. while hidle is cleared, data written to the htx will be transmitted ?s is.?if the shi completes transmitting a word and there is no new data in the htx, the clock will be suspended after sampling ack. hidle selects the kind of acknowledge that the receiver sends after correct reception of a byte. if hidle is cleared, the reception will be acknowledged by sending a ??bit on the sda line at the ack clock tick. if hidle is set, the reception will not be acknowledged (a ??bit is sent). it is used to signal an end-of-data to a slave transmitter by not generating an ack on the last byte. as a result, the slave transmitter must release the sda line to allow the master to generate the stop event. if the shi completes receiving a word and the hrx fifo is full, the clock will be suspended before transmitting an ack. while hidle is cleared the bus is busy, that is, the start event was sent but no stop event was generated. setting hidle will cause a stop event. hidle is set while the shi is not in the i 2 c master mode. hidle is set during hardware reset, software reset, individual reset, and while the chip is in the stop state. table 5-5 h req function in shi slave modes hrqe1 hrqe0 hreq pin operation 0 0 high impedance 0 1 asserted if iosr is ready to receive a new word 1 0 asserted if iosr is ready to transmit a new word 11 i 2 c: asserted if iosr is ready to transmit or receive spi: asserted if iosr is ready to transmit and receive f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-16 dsp56004 user? manual motorola serial host interface serial host interface programming model 5.3.6.9 hcsr bus-error interrupt enable (hbie)?it 10 the read/write hcsr bus-error interrupt enable (hbie) control bit is used to enable the shi bus-error interrupt. if hbie is cleared, bus-error interrupts are disabled, and the hber status bit must be polled to determine if an shi bus error occurred. if both hbie and hber are set, the shi will request shi bus-error interrupt service from the interrupt controller. hbie is cleared by hardware reset and software reset. note: clearing hbie will mask a pending bus-error interrupt only after a one-instruction-cycle delay. if hbie is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears hbie and the rti instruction at the end of the interrupt service routine. 5.3.6.10 hcsr transmit-interrupt enable (htie)?it 11 the read/write hcsr transmit-interrupt enable (htie) control bit is used to enable the shi transmit data interrupts. if htie is cleared, transmit interrupts are disabled, and the htde status bit must be polled to determine if the shi transmit-data register is empty. if both htie and htde are set and htue is cleared, the shi will request shi transmit-data interrupt service from the interrupt controller. if both htie and htue are set, the shi will request shi transmit-underrun-error interrupt service from the interrupt controller. htie is cleared by hardware reset and software reset. note: clearing htie will mask a pending transmit interrupt only after a one-instruction cycle-delay. if htie is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears htie and the rti instruction at the end of the interrupt service routine. 5.3.6.11 hcsr receive interrupt enable (hrie[1:0])?its 13?2 the read/write hcsr receive interrupt enable (hrie[1:0]) control bits are used to enable the shi receive-data interrupts. if hrie[1:0] are cleared, receive interrupts are disabled, and the hrne and hrff (bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive fifo. if hrie[1:0] are not cleared, receive interrupts will be generated according to table 5-6 . hrie[1:0] are cleared by hardware reset and software reset. note: clearing hrie[1:0] will mask a pending receive interrupt only after a one-instruction-cycle delay. if hrie[1:0] are cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears hrie[1:0] and the rti instruction at the end of the interrupt service routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface serial host interface programming model motorola dsp56004 user? manual 5-17 5.3.6.12 hcsr host transmit underrun error (htue)?it 14 the read-only status bit host transmit underrun error (htue) indicates that a transmit-underrun error occurred. transmit-underrun errors can occur only when operating in a slave mode (in a master mode, transmission occurs in an on-demand basis and no underrun can occur). it is set when both the shift register and the htx register are empty and the external master begins reading the next word: when operating in the i 2 c mode, htue is set in the falling edge of the ack bit. in this case, the shi will retransmit the previously transmitted word. when operating in the spi mode, htue is set at the first clock edge if cpha = 1; it is set at the assertion of ss if cpha = 0. if a transmit interrupt occurs with htue set, the transmit-underrun interrupt vector will be generated. if a transmit interrupt occurs with htue cleared, the regular transmit-data interrupt vector will be generated. htue is cleared by reading the hcsr and then writing to the htx register. htue is cleared by hardware reset, software reset, shi individual reset, and during the stop state. 5.3.6.13 hcsr host transmit data empty (htde)?it 15 the read-only status bit host transmit data empty (htde) indicates that the htx register is empty and can be written by the dsp. htde is set when the data word is transferred from htx to the shift register, except for a special case in spi master mode when cpha = 0 (see hckr). when operating in the spi master mode with cpha = 0, htde is set after the end of the data word transmission. htde is cleared when htx is written by the dsp. htde is set by hardware reset, software reset, shi individual reset, and during the stop state. 5.3.6.14 host receive fifo not empty (hrne)?it 17 the read-only status bit host receive fifo not empty (hrne) indicates that the host receive fifo (hrx) contains at least one data word. hrne is set when the fifo is not empty. hrne is cleared when hrx is read by the dsp, reducing the table 5-6 hcsr receive interrupt enable bits hrie[1:0] interrupt condition 00 disabled n.a. 01 receive fifo not empty receive overrun error hrne = 1 & hroe = 0 hroe = 1 10 reserved n.a. 11 receive fifo full receive overrun error hrff = 1 & hroe = 0 hroe = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-18 dsp56004 user? manual motorola serial host interface serial host interface programming model number of words in the fifo to 0. hrne is cleared during hardware reset, software reset, shi individual reset, and during the stop state. 5.3.6.15 host receive fifo full (hrff)?it 19 the read-only status bit host receive fifo full (hrff) indicates that the host receive fifo (hrx) is full. hrff is set when the hrx fifo is full. hrff is cleared when hrx is read by the dsp and at least one place is available in the fifo. hrff is cleared by hardware reset, software reset, shi individual reset, and during the stop state. 5.3.6.16 host receive overrun error (hroe)?it 20 the read-only status bit host receive overrun error (hroe) indicates that a data-receive overrun error occurred. receive-overrun errors cannot occur when operating in the i 2 c master mode, since the clock is suspended if the receive fifo is full. hroe is set when the shift register (iosr) is filled and ready to transfer the data word to the hrx fifo and the fifo is already full (hrff is set). when a receive-overrun error occurs, the shift register is not transferred to the fifo. if a receive interrupt occurs with hroe set, the receive-overrun interrupt vector will be generated. if a receive interrupt occurs with hroe cleared, the regular receive-data interrupt vector will be generated. hroe is cleared by reading the hcsr register with hroe set, followed by reading hrx. hroe is cleared by hardware reset, software reset, shi individual reset, and during the stop state. 5.3.6.17 host bus error (hber)?it 21 the read-only status bit host bus error (hber) indicates that an shi bus error occurred when operating as a master (hmst set). in i 2 c mode, hber is set if the transmitter does not receive an acknowledge after a byte is transferred; in this case, a stop event will be generated and then transmission will be suspended. in spi mode, the bit is set if ss is asserted; in this case, transmission is suspended at the end of transmission of the current word. hber is cleared only by hardware reset, software reset, shi individual reset, and during the stop state. 5.3.6.18 hcsr host busy (hbusy)?it 22 the read-only status bit host busy (hbusy) indicates that the i 2 c bus is busy (when in the i 2 c mode) or that the shi itself is busy (when in the spi mode). when operating in the i 2 c mode, hbusy is set after the shi detects a start event and remains set until a stop event is detected. when operating in the spi slave mode, hbusy is set while ss is asserted. when operating in the spi master mode, hbusy is set if the htx register is not empty or if the iosr shift register is not empty. hbusy is cleared otherwise. hbusy is cleared by hardware reset, software reset, shi individual reset, and during the stop state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface characteristics of the spi bus motorola dsp56004 user? manual 5-19 5.4 characteristics of the spi bus the spi bus consists of two serial data lines, master in, slave out (miso), master out, slave in (mosi), a serial clock line (sck), and a slave select line (ss ). during an spi transfer, a byte is shifted out one data pin while a different byte is simultaneously shifted in through a second data pin. it can be viewed as two 8-bit shift registers connected together in a circular manner, where one shift register is located on the master side and the other on the slave side. thus, the data bytes in the master and slave are effectively exchanged. the miso and mosi data pins are used for transmitting and receiving serial data. when the spi is configured as a master, miso is the master data input line, and mosi is the master data output line. when the spi is configured as a slave, these pins reverse functionality. clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. when the spi is configured as a master, the control bits in the hckr select the appropriate clock rate, as well as the desired clock polarity and phase format (see figure 5-6 on page 5-11). the slave select (ss ) line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activity (they keep their miso output pin in the high-impedance state). when the shi is configured as an spi master, the ss line should be held high. if the ss line is driven low when the shi is in spi master mode, a bus error will be generated (the hcsr hber bit will be set). 5.5 characteristics of the i 2 c bus the i 2 c serial bus consists of two bi-directional lines, one for data signals (serial data and acknowledge?da) and one for clock signals (serial clock?cl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-20 dsp56004 user? manual motorola serial host interface characteristics of the i 2 c bus 5.5.1 overview the i 2 c bus protocol must conform to the following rules: data transfer may be initiated only when the bus is not busy during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line when the clock line is high will be interpreted as control signals (see figure 5-7 ) accordingly, the i 2 c bus protocol defines the following events: bus not busy: both data and clock lines remain high start data transfer: the start event is defined as a change in the state of the data line, from high to low, while the clock is high (see figure 5-8 ) stop data transfer: the stop event is defined as a change in the state of the data line, from low to high, while the clock is high (see figure 5-8 ) data valid: the data line contains valid data when, after a start event, the data line is stable for the duration of the high period of the clock signal; the data on the line may be changed during the low period of the clock signal; there is one clock pulse per bit of data figure 5-7 i 2 c bit transfer figure 5-8 i 2 c start and stop events sda scl data line stable: data valid change of data allowed aa0422k s p start event stop event sda scl aa0423 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface characteristics of the i 2 c bus motorola dsp56004 user? manual 5-21 within the i 2 c bus specifications, a low-speed mode (2 khz clock rate) and a high-speed mode (100 khz clock rate) are defined. the shi operates in the high-speed mode only. by definition, a device that generates a signal is called a ?ransmitter,?and a device that receives a signal from a transmitter is called a ?eceiver.?the device that controls the signal is called the ?aster?and the devices that are controlled by the master are called ?laves. each 8-bit word is followed by one acknowledge bit. this acknowledge bit is a high level put on the bus by the transmitter when the master generates an extra acknowledge-related clock pulse. a slave receiver that is addressed is obliged to generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse (see figure 5-9 ). a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master generation of the stop event. handshaking may also be accomplished by use of the clock synchronizing mechanism. slaves can hold the scl line low, after receiving and acknowledging a byte, to force the master into a wait state until the slave is ready for the next byte transfer. the shi supports this feature when operating as a master and will wait until the slave releases the scl line before proceeding with the data transfer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-22 dsp56004 user? manual motorola serial host interface shi programming considerations 5.5.2 i 2 c data transfer formats i 2 c bus data transfers follow the following format: after the start event, a slave address is sent. this address is 7 bits wide. the eighth bit is a data direction bit (r/w ) 0?indicates a transmission (write), and ??indicates a request for data (read). a data transfer is always terminated by a stop event generated by the master. however, if the master still wishes to communicate on the bus, it can generate another start event, and address another slave without first generating a stop event (this feature is not supported by the shi when operating as an i 2 c master). this method is also used to provide indivisible data transfers. various combinations of read/write formats are illustrated in figure 5-10 and figure 5-11 . note that the first data byte in a write-bus cycle can be used as a user-defined control byte (e.g., to determine the location to which the subsequent data bytes should be transferred). 5.6 shi programming considerations the shi supports both spi and i 2 c bus protocols and can be configured to operate as a slave or a single master device. once the operating mode is selected, the shi may communicate with an external device by receiving and/or transmitting data. before changing the shi operational mode, an shi individual reset should be generated by clearing the hen bit. the following paragraphs describe programming considerations for each operational mode. figure 5-9 acknowledgment on the i 2 c bus start event clock pulse for acknowledgment s 12 89 scl from master data output by transmitter data output by receiver aa0424 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface shi programming considerations motorola dsp56004 user? manual 5-23 5.6.1 spi slave mode the spi slave mode is entered by enabling the shi (hen = 1), selecting the spi mode (hi 2 c = 0), and selecting the slave mode of operation (hmst = 0). the programmer should verify that the cpha and cpol bits (in the hckr register) correspond to the external host clock phase and polarity. other hckr bits are ignored. when configured in the spi slave mode, the shi external pins operate as follows: sck/scl is the sck serial clock input. miso/sda is the miso serial data output. mosi/ha0 is the mosi serial data input. ?s /ha2 is the ss slave select input. hreq is the host request output. in the spi slave mode, a receive, transmit, or full-duplex data transfer may be performed. actually, the interface simultaneously performs both data receive and figure 5-10 i 2 c bus protocol for host write cycle figure 5-11 i 2 c bus protocol for host read cycle saa 0 slave address r/w s, p a start start or bit stop bit slave ack from slave ack from slave ack from n = 0 to m data bytes first data byte data byte aa0425 saa 1 slave address r/w p 1 start stop bit bit slave ack from master ack from no ack data byte n = 0 to m data bytes last data byte from master aa0426 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-24 dsp56004 user? manual motorola serial host interface shi programming considerations transmit. the status bits of both receive and transmit paths are active; however, the programmer may disable undesired interrupts and ignore non-relevant status bits. it is recommended that an shi individual reset (hen cleared) be generated before beginning data reception in order to reset the hrx fifo to its initial (empty) state (e.g., when switching from transmit to receive data). if a write to htx occurs, its contents are transferred to iosr between data word transfers. the iosr data is shifted out (via miso) and received data is shifted in (via mosi). the dsp may write htx if the htde status bit is set. if no writes to htx occurred, the contents of htx are not transferred to iosr, so the data that is shifted out when receiving is the same as the data present in the iosr shift register at the time. the hrx fifo contains valid receive data, which may be read by the dsp, if the hrne status bit is set. the hreq output pin, if enabled for receive (hrqe1-hrqe0 = 01), is asserted when the iosr is ready for receive and the hrx fifo is not full; this operation guarantees that the next received data word will be stored in the fifo. the hreq output pin, if enabled for transmit (hrqe1-hrqe0 = 10), is asserted when the iosr is loaded from htx with a new data word to transfer. if hreq is enabled for both transmit and receive (hrqe1-hrqe0 = 11), it is asserted when the receive and transmit conditions are true simultaneously. hreq is deasserted at the first clock pulse of the next data word transfer. the hreq line may be used to interrupt the external master. connecting the hreq line between two shi-equipped dsps, one operating as an spi master and the other as an spi slave, enables full hardware handshaking if operating with cpha = 1. the ss line should be kept asserted during a data word transfer. if the ss line is deasserted before the end of the data word transfer, the transfer is aborted and the received data word is lost. 5.6.2 spi master mode the spi master mode is initiated by enabling the shi (hen = 1), selecting the spi mode (hi 2 c = 0), and selecting the master mode of operation (hmst = 1). before enabling the shi as an spi master, the programmer should program the proper clock rate, phase, and polarity in hckr. when configured in the spi master mode, the shi external pins operate as follows: sck/scl is the sck serial clock output. miso/sda is the miso serial data input. mosi/ha0 is the mosi serial data output. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface shi programming considerations motorola dsp56004 user? manual 5-25 ?s /ha2 is the ss input. it should be kept deasserted (high) for proper operation. hreq is the host request input. the external slave can be selected either by using external logic or by activating a gpio pin connected to its ss pin. however, the ss input pin of the spi master should be held deasserted (high) for proper operation. if the spi master ss pin is asserted, the bus error status bit (hber) is set. if the bus error interrupt enable (hbie) bit is also set, the shi will request an shi bus error interrupt service from the dsp interrupt controller. in the spi master mode the dsp must write to htx in order to perform a receive, a transmit, or a full-duplex data transfer. actually, the interface performs simultaneous data receive and transmit. the status bits of both receive and transmit paths are active; however, the programmer may disable undesired interrupts and ignore non-relevant status bits. in a data transfer, the htx is transferred to iosr, clock pulses are generated, the iosr data is shifted out (via mosi) and received data is shifted in (via miso). the dsp programmer may write htx (if the htde status bit is set) to initiate the transfer of the next word. the hrx fifo contains valid receive data, which may be read by the dsp, if the hrne status bit is set. it is recommended that an shi individual reset (hen cleared) be generated before beginning data reception in order to reset the receive fifo to its initial (empty) state (e.g., when switching from transmit to receive data). the hreq input pin is ignored by the spi master if hrqe[1:0] are cleared, and considered if either of them is set. when asserted by the slave, hreq indicates that the external slave is ready for the next data transfer. as a result, the spi master sends clock pulses for the full data word transfer. hreq is deasserted by the external slave at the first clock pulse of the new data transfer. when deasserted, hreq will prevent the clock generation of the next data word transfer until it is asserted again. connecting the hreq line between two shi-equipped dsps, one operating as an spi master and the other as an spi slave, enables full hardware handshaking if cpha = 1. for cpha = 0, hreq should be disabled by clearing hrqe[1:0]. 5.6.3 i 2 c slave mode the i 2 c slave mode is entered by enabling the shi (hen = 1), selecting the i 2 c mode (hi 2 c = 1), and selecting the slave mode of operation (hmst = 0). in this operational mode the contents of hckr are ignored. when configured in the i 2 c slave mode, the shi external pins operate as follows: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-26 dsp56004 user? manual motorola serial host interface shi programming considerations sck/scl is the scl serial clock input. miso/sda is the sda open drain serial data line. mosi/ha0 is the ha0 slave address input. ?s /ha2 is the ha2 slave address input. hreq is the host request output. when the shi is enabled and configured in the i 2 c slave mode, the shi controller inspects the sda and scl lines to detect a start event. upon detection of the start event, the shi receives the slave address byte and enables the slave address recognition unit. if the slave address byte was not identified as its personal address, the shi controller will fail to acknowledge this byte by not driving low the sda line at the ninth clock pulse (ack = 1). however, it continues to poll the sda and scl lines to detect a new start event. if the personal slave address was correctly identified, the slave address byte is acknowledged (ack = 0 is sent) and a receive/transmit session is initiated according to the eighth bit of the received slave address byte (the r/w bit). 5.6.3.1 receive data in i 2 c slave mode a receive session is initiated when the personal slave address has been correctly identified and the r/w bit of the received slave address byte has been cleared. following a receive initiation, data in the sda line is shifted into iosr msb first. following each received byte, an acknowledge (ack = 0) is sent at the ninth clock pulse via the sda line. data is acknowledged bytewise, as required by the i 2 c bus protocol, and is transferred to the hrx fifo when the complete word (according to hm[1:0]) is filled into iosr. it is the responsibility of the programmer to select the correct number of bytes in an i 2 c frame so that they fit in a complete number of words. for this purpose, the slave address byte does not count as part of the data, and therefore, it is treated separately. in a receive session, only the receive path is enabled and htx to iosr transfers are inhibited. the hrx fifo contains valid data, which may be read by the dsp if the hrne status bit is set. when the hrx fifo is full and iosr is filled, an overrun error occurs and the hroe status bit is set. in this case, the last received byte will not be acknowledged (ack = 1 is sent) and the word in the iosr will not be transferred to the hrx fifo. this may inform the external i 2 c master of the occurrence of an overrun error on the slave side. consequently the i 2 c master may terminate this session by generating a stop event. the hreq output pin, if enabled for receive (hrqe[1:0] = 01), is asserted when the iosr is ready to receive and the hrx fifo is not full; this operation guarantees that the next received data word will be stored in the fifo. hreq is deasserted at the first clock pulse of the next received word. the hreq line may be used to interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface shi programming considerations motorola dsp56004 user? manual 5-27 the external i 2 c master. connecting the hreq line between two shi-equipped dsps, one operating as an i 2 c master and the other as an i 2 c slave, enables full hardware handshaking. 5.6.3.2 transmit data in i 2 c slave mode a transmit session is initiated when the personal slave address has been correctly identified and the r/w bit of the received slave address byte has been set. following a transmit initiation, the iosr is loaded from htx (assuming the latter was not empty) and its contents are shifted out, msb-first, on the sda line. following each transmitted byte, the shi controller samples the sda line at the ninth clock pulse, and inspects the ack status. if the transmitted byte was acknowledged (ack = 0), the shi controller continues and transmits the next byte. however, if it was not acknowledged (ack = 1), the transmit session is stopped and the sda line is released. consequently, the external master may generate a stop event in order to terminate the session. htx contents are transferred to iosr when the complete word (according to hm[1:0]) has been shifted out. it is, therefore, the responsibility of the programmer to select the correct number of bytes in an i 2 c frame so that they fit in a complete number of words. for this purpose, the slave address byte does not count as part of the data, and therefore, it is treated separately. in a transmit session, only the transmit path is enabled and the iosr-to-hrx fifo transfers are inhibited. when the htx transfers its valid data word to iosr, the htde status bit is set and the dsp may write a new data word to htx. if both iosr and htx are empty, an underrun condition occurs, setting the htue status bit; if this occurs, the previous word will be retransmitted. the hreq output pin, if enabled for transmit (hrqe[1:0] = 10), is asserted when htx is transferred to iosr for transmission. when asserted, hreq indicates that the slave is ready to transmit the next data word. hreq is deasserted at the first clock pulse of the next transmitted data word. the hreq line may be used to interrupt the external i 2 c master. connecting the hreq line between two shi-equipped dsps, one operating as an i 2 c master and the other as an i 2 c slave, enables full hardware handshaking. 5.6.4 i 2 c master mode the i 2 c master mode is entered by enabling the shi (hen = 1), selecting the i 2 c mode (hi 2 c = 1) and selecting the master mode of operation (hmst = 1). before f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-28 dsp56004 user? manual motorola serial host interface shi programming considerations enabling the shi as an i 2 c master, the programmer should program the appropriate clock rate in hckr. when configured in the i 2 c master mode, the shi external pins operate as follows: sck/scl is the scl serial clock output miso/sda is the sda open drain serial data line mosi/ha0 is the ha0 slave address input ?s /ha2 is the ha2 slave address input hreq is the host request input in the i 2 c master mode, a data transfer session is always initiated by the dsp by writing to the htx register when hidle is set. this condition ensures that the data byte written to htx will be interpreted as being a slave address byte. this data byte must specify the slave address to be selected and the requested data transfer direction. note that the slave address byte should be located in the high portion of the data word, whereas the middle and low portions are ignored. only one byte (the slave address byte) will be shifted out, independent of the word length selected by the hm[1:0] bits. in order for the dsp to initiate a data transfer the following actions are to be performed: the dsp tests the hidle status bit. if the hidle status bit is set, the dsp writes the slave address and the r/w bit to the most significant byte of htx. the shi generates a start event. the shi transmits one byte only, internally samples the r/w direction bit (last bit), and accordingly initiates a receive or transmit session. the shi inspects the sda level at the ninth clock pulse to determine the ack value. if acknowledged (ack = 0), it starts its receive or transmit session according to the sampled r/w value. if not acknowledged (ack = 1), the hber status bit in hcsr is set, which will cause an shi bus error interrupt request if hbie is set, and a stop event will be generated. the hreq input pin is ignored by the i 2 c master if hrqe1 and hrqe0 are cleared, and considered if either of them is set. when asserted, hreq indicates that the external slave is ready for the next data transfer. as a result, the i 2 c master sends clock pulses for the full data word transfer. hreq is deasserted by the external slave at the first clock pulse of the next data transfer. when deasserted, hreq will prevent f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial host interface shi programming considerations motorola dsp56004 user? manual 5-29 the clock generation of the next data word transfer until it is asserted again. connecting the hreq line between two shi-equipped dsps, one operating as an i 2 c master and the other as an i 2 c slave, enables full hardware handshaking. 5.6.4.1 receive data in i 2 c master mode a receive session is initiated if the r/w direction bit of the transmitted slave address byte is set. following a receive initiation, data in sda line is shifted into iosr msb first. following each received byte, an acknowledge (ack = 0) is sent at the ninth clock pulse via the sda line if the hidle control bit is cleared. data is acknowledged bytewise, as required by the i 2 c bus protocol, and is transferred to the hrx fifo when the complete word (according to hm[1:0]) is filled into iosr. it is the responsibility of the programmer to select the correct number of bytes in an i 2 c frame so that they fit in a complete number of words. for this purpose, the slave address byte does not count as part of the data, and therefore, it is treated separately. if the i 2 c slave transmitter is acknowledged, it should transmit the next data byte. in order to terminate the receive session, the programmer should set the hidle bit at the last required data word. as a result, the last byte of the next received data word is not acknowledged, the slave transmitter releases the sda line, and the shi generates the stop event and terminates the session. in a receive session, only the receive path is enabled and the htx-to-iosr transfers are inhibited. if the hrne status bit is set, the hrx fifo contains valid data, which may be read by the dsp. when the hrx fifo is full, the shi suspends the serial clock just before acknowledge. in this case, the clock will be reactivated when the fifo is read (the shi gives an ack = 0 and proceeds receiving) or when hidle is set (the shi gives ack = 1, generates the stop event, and ends the receive session). 5.6.4.2 transmit data in i 2 c master mode a transmit session is initiated if the r/w direction bit of the transmitted slave address byte is cleared. following a transmit initiation, the iosr is loaded from htx (assuming htx is not empty) and its contents are shifted out, msb-first, on the sda line. following each transmitted byte, the shi controller samples the sda line at the ninth clock pulse, and inspects the ack status. if the transmitted byte was acknowledged (ack = 0), the shi controller continues transmitting the next byte. however, if it was not acknowledged (ack = 1), the hber status bit is set to inform the dsp side that a bus error (or overrun, or any other exception in the slave device) has occurred. consequently, the i 2 c master generates a stop event and terminates the session. htx contents are transferred to the iosr when the complete word (according to hm[1:0]) has been shifted out. it is, therefore, the responsibility of the programmer to select the right number of bytes in an i 2 c frame so that they fit in a complete number f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-30 dsp56004 user? manual motorola serial host interface shi programming considerations of words. remember that for this purpose, the slave address byte does not count as part of the data. in a transmit session, only the transmit path is enabled and the iosr-to-hrx fifo transfers are inhibited. when the htx transfers its valid data word to the iosr, the htde status bit is set and the dsp may write a new data word to htx. if both iosr and htx are empty, the shi will suspend the serial clock until new data is written into htx (when the shi proceeds with the transmit session) or hidle is set (the shi reactivates the clock to generate the stop event and terminate the transmit session). 5.6.5 shi operation during stop the shi operation cannot continue when the dsp is in the stop state, since no dsp clocks are active. while the dsp is in the stop state, the shi will remain in the individual reset state. while in the individual reset state: shi input pins are inhibited output and bidirectional pins are disabled (high impedance) the hcsr status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset the hcsr and hckr control bits are not affected it is recommended that the shi be disabled before entering the stop state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual 6-1 section 6 serial audio interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-2 dsp56004 user? manual motorola serial audio interface 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 serial audio interface internal architecture 6-4 6.3 serial audio interface programming model . . . 6-8 6.4 programming considerations . . . . . . . . . . . . . . . . 6-24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface introduction motorola dsp56004 user? manual 6-3 6.1 introduction the dsp communicates with data sources and sinks through its serial audio interface (sai). the sai is a synchronous serial interface dedicated for audio data transfers. it provides a full duplex serial port for serial connection with a variety of audio devices such as analog-to-digital (a/d) converters, digital-to-analog (d/a) converters, cd devices, etc. the sai implements a wide range of serial data formats currently in use by audio manufacturers. examples are: ? 2 s (inter integrated-circuit sound) format (philips) cdp format (sony) mec format (matsushita) most industry-standard a/d and d/a the sai consists of independent transmit and receive sections and a shared baud-rate generator. the transmitter and receiver sections may each operate in either the master or slave mode. in the master mode the serial clock and the word select lines are driven internally according to the baud-rate generator programming. in the slave mode these signals are supplied from an external source. the transmitter consists of three transmit-data registers, three fully synchronized output- shift registers, and three serial-data output lines controlled by one transmitter controller. this permits data transmission to one, two, or three stereo audio devices simultaneously. the receiver consists of two receive-data registers, two fully synchronized input-shift registers, and two serial data input lines controlled by one receiver controller. this permits data reception from one or two stereo audio devices simultaneously. the following is a short list of the sai features: programmable serial clock generator with high resolution: f sck = f osc /2i (for i > 1) maximum external serial clock rate equal to one third of the dsp core clock separate transmit and receive sections master or slave operating modes three synchronized data transmission lines two synchronized data reception lines double-buffered f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-4 dsp56004 user? manual motorola serial audio interface serial audio interface internal architecture user programmable to support a wide variety of serial audio formats three receive interrupt vectors: receive left channel, receive right channel, and receive with exception three transmit interrupt vectors: transmit left channel, transmit right channel, and transmit with exception 6.2 serial audio interface internal architecture the sai is functionally divided into three parts: the baud-rate generator, the receiver section, and the transmitter section. the receive and transmit sections are completely independent and can operate concurrently or separately. the following paragraphs describe the operation of these sections. 6.2.1 baud-rate generator the baud-rate generator produces the internal serial clock for the sai if either or both of the receiver and transmitter sections are configured in the master mode. the baud-rate generator is disabled if both receiver and transmitter sections are configured as slaves. figure 6-1 illustrates the internal clock path connections. the receiver and transmitter clocks can be internal or external depending on the configuration of the receive master (rmst) and transmit master (tmst) control bits. figure 6-1 sai baud-rate generator block diagram tx tmst tmst = 0 tmst = 1 sckt rx rmst rmst = 0 rmst = 1 sckr divider divide by 1 or divide by 8 divide by 1 to divide by 256 prescale psr pm0?m7 rclock tclock f osc internal clock divide by 2 aa0427k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface internal architecture motorola dsp56004 user? manual 6-5 6.2.2 receive section overview the receive section contains two receivers and consists of a 16-bit control/status register, two 24-bit shift registers, and two 24-bit data registers. these two receivers share the same control mechanism, therefore the bit clock, word select line, and all control signals generated in the receive section simultaneously affect both receivers. the receiver section can be configured as a master driving its bit clock and word select lines from the internal baud-rate generator, or as a slave receiving these signals from an external source. when both receivers are disabled, the receive controller becomes idle, the status bits rldf and rrdf (see section 6.3.2 receiver control/status register (rcs) , below) are cleared, and the receive section external pins are tri-stated. the block diagram of the receiver section is shown in figure 6-2 . the 24-bit shift registers receive the incoming data from the serial data in pins (sdi0 and sdi1, or sdix). data is shifted in at the transitions of the serial receive clock sckr. data is assumed to be received msb first if rdir is cleared, and lsb first if rdir is set. data is transferred to the sai receive data registers after 16, 24, or 32 bits have been shifted in, as determined by the word length control bits rwl1 and rwl0. a special control mechanism is used to emulate a 32-bit shift register in the event that the word length is defined as 32 bits. this is done by disabling eight data shifts at the beginning/end of the data word transfer, according to the rdwt bit in the rcs register. these shift registers cannot be directly accessed by the dsp. figure 6-2 sai receive section block diagram global data bus (gdb) rx control/status (rcs) rx controller rclock 0 15 rx0 shift register rx1 data register rx1 shift register sdi1 rx0 data register sdi0 status control 0 23 23 23 23 0 0 0 aa0428 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-6 dsp56004 user? manual motorola serial audio interface serial audio interface internal architecture 6.2.3 sai transmit section overview the transmit section contains three transmitters and consists of a 16-bit control/status register, three 24-bit shift registers, and three 24-bit data registers. these three transmitters are controlled by the same control mechanism, therefore, the bit clock, word select line, and all control signals generated in the transmit section equally affect all three transmitters. the transmit section can be configured as a master driving its bit clock and word select lines from the internal baud-rate generator, or as a slave receiving these signals from an external source. each of the three transmitters can be enabled separately. when a transmitter is disabled, its associated serial data out (sdo) pin goes to high level. when all transmitters are disabled, the transmit controller becomes idle, the status bits trde and tlde are cleared, and the transmit section external pins, word select transmit (wst) and serial clock transmit (sckt), are tri-stated. the transmitter section is illustrated in figure 6-3 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface internal architecture motorola dsp56004 user? manual 6-7 . the transmitter section data path consists of three fully synchronized sets of data and shift registers capable of operating simultaneously. in each set, the 24-bit shift register contains the data being transmitted. data is shifted out to the associated sdo pin at the transitions of the serial transmit clock sckt. data is shifted out msb first if tdir is cleared, and lsb first if tdir is set. the number of bits shifted out before the shift register is considered empty and ready to be reloaded can be 16, 24, or 32 bits as determined by the twl1 and twl0 control bits in the tcs register. a special control mechanism is used to emulate a 32-bit shift register if the word length is defined as 32 bits. this is done by enabling eight data shifts at the beginning/end of the data word transfer, according to the tdwe bit in the tcs register. these shift registers cannot be directly accessed by the dsp. figure 6-3 sai transmit section block diagram tx0 shift register global data bus (gdb) transmit control/status (tcs) tx1 data register tx1 shift register transmit controller tclock sdo1 tx0 data register sdo0 status control 0 15 0 23 23 23 23 0 0 0 tx2 data register tx2 shift register sdo2 23 0 23 0 aa0429k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-8 dsp56004 user? manual motorola serial audio interface serial audio interface programming model 6.3 serial audio interface programming model the serial audio interface registers that are available to the programmer are shown in figure 6-4 . the registers are described in the following paragraphs. the sai interrupt vectors can be located in either of two different regions in memory. the transmit interrupt vector locations are controlled by txil bit in the transmit control status (tcs) register. similarly, the receive interrupt vector locations are controlled by rxil bit in the receive control status (rcs) register. the interrupt vector locations for the sai are shown in table 6-1 . the interrupts generated by the sai are prioritized as shown in table 6-2 . figure 6-4 sai registers pm0 0 1 pm2 2 pm3 3 pm4 4 5 pm6 6 pm7 7 psr 8 9 10 11 12 13 14 15 baud rate control register (brc) r0en 0 1 rmst 2 rwl0 3 rwl1 4 5 rdir 6 rlrs 7 rckp 8 rrel 9 rdwt 10 rxie 11 12 13 rldf 14 rrdf 15 receive control/status register (rcs) t0en 0 1 tmst 2 twl0 3 twl1 4 5 tdir 6 tlrs 7 tckp 8 trel 9 tdwe 10 txie 11 12 13 tlde 14 trde 15 transmit control/status register (tcs) t1en pm1 pm5 reserved bit(s) t2en r1en receiver 0 data register 0 23 receiver 1 data register 0 23 transmitter 0 data register 0 23 transmitter 1 data register 0 23 transmitter 2 data register 0 23 read-only read-only write-only write-only write-only x: $ffe2 x: $ffe3 x: $ffe5 x: $ffe6 x: $ffe7 x: $ffe0 x: $ffe1 x: $ffe4 txil rxil aa0430k 23 16 23 16 23 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-9 6.3.1 baud rate control register (brc) the serial clock frequency is determined by the control bits in the baud rate control register (brc) as described in the following paragraphs. the brc is illustrated in figure 6-4 on page 6-8. the maximum allowed internally generated bit clock frequency is f osc /4 and the maximum allowed external bit clock frequency is f osc /3. brc bits should be modified only when the baud-rate generator is disabled (i.e., when both receiver and transmitter sections are defined as slaves or when both are in the individual reset state); otherwise improper operation may result. when read by the dsp, the brc appears on the two low-order bytes of the 24-bit word, and the high-order byte is read as 0s. the brc is cleared during hardware reset and software reset. table 6-1 sai interrupt vector locations interrupt txil = 0 txil = 1 rxil = 0 rxil = 1 left channel transmit p: $0010 p: $0040 right channel transmit p: $0012 p: $0042 transmit exception p: $0014 p: $0044 left channel receive p: $0016 p: $0046 right channel receive p: $0018 p: $0048 receive exception p: $001a p: $004a table 6-2 sai internal interrupt priorities priority interrupt highest sai receive sai transmit sai left channel receive sai left channel transmit sai right channel receive lowest sai right channel transmit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-10 dsp56004 user? manual motorola serial audio interface serial audio interface programming model 6.3.1.1 prescale modulus select (pm[7:0])?its 7? the pm[7:0] bits specify the divide ratio of the prescale divider in the sai baud-rate generator. a divide ratio between 1 and 256 (pm[7:0] = $00 to $ff) may be selected. the pm[7:0] bits are cleared during hardware reset and software reset. note: the programmer should not use the combination psr = 1 and pm[7:0] = 00000000, since it may cause synchronization problems and improper operation (it is considered an illegal combination). 6.3.1.2 prescaler range (psr)?it 8 the prescaler range (psr) bit controls a fixed divide-by-eight prescaler connected in series with the variable prescale divider. this bit is used to extend the range of the prescaler for those cases in which a slower clock rate is desired. when psr is set, the fixed prescaler is bypassed. when psr is cleared, the fixed divide-by-eight prescaler is operational. the psr bit is cleared during hardware reset and software reset. 6.3.1.3 brc reserved bits?its 15? bits 15? in the brc are reserved and unused. they read as 0s and should be written with 0s for future compatibility. 6.3.2 receiver control/status register (rcs) the receiver control/status register (rcs) is a 16-bit read/write control/status register used to direct the operation of the receive section in the sai (see figure 6-4 on page 6-8). the control bits in the rcs determine the serial format of the data transfers, whereas the status bits of the rcs are used by the dsp programmer to interrogate the status of the receiver. receiver-enable and interrupt-enable bits are also provided in the rcs. when read by the dsp, the rcs appears on the two low-order bytes of the 24-bit word, and the high-order byte is read as 0s. hardware reset and software reset clear all the bits in the rcs. if both r0en and r1en bits are cleared, the receiver section is disabled and it enters the individual reset state. the individual reset state is entered 1 instruction cycle after bits r0en and r1en are cleared. while in the stop or individual reset state, the status bits in rcs are also cleared. stop or individual reset do not affect the rcs control bits. the programmer should change the rcs control bits (except for rxie) only while the receiver section is in the individual reset state (i.e., disabled), otherwise improper operation may result. the rcs bits are described in the following paragraphs. 6.3.2.1 rcs receiver 0 enable (r0en)?it 0 the read/write receiver 0 enable (r0en) control bit enables the operation of sai receiver 0. when r0en is set, receiver 0 is enabled. when r0en is cleared, receiver 0 is disabled. if both r0en and r1en are cleared, the receiver section is disabled, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-11 which is equivalent to the individual reset state. the r0en bit is cleared during hardware reset and software reset. 6.3.2.2 rcs receiver 1 enable (r1en)?it 1 the read/write receiver 1 enable (r1en) control bit enables the operation of sai receiver 1. when r1en is set, receiver 1 is enabled. when r1en is cleared, receiver 1 is disabled. if both r0en and r1en are cleared, the receiver section is disabled, which is equivalent to the individual reset state. the r1en bit is cleared during hardware reset and software reset. 6.3.2.3 rcs reserved bit?its 13 and 2 bits 13 and 2 in the rcs are reserved and unused. they read as 0s and should be written with 0s for future compatibility. 6.3.2.4 rcs receiver master (rmst)?it 3 the read/write control bit receiver master (rmst) switches the operation of the receiver section between master and slave modes. when rmst is set, the sai receiver section is configured as a master. in the master mode the receiver drives the sckr and wsr pins. when rmst is cleared, the sai receiver section is configured as a slave. in the slave mode, the sckr and wsr pins are driven from an external source. the rmst bit is cleared during hardware reset and software reset. 6.3.2.5 rcs receiver word length control (rwl[1:0])?its 4 and 5 the read/write receiver word length (rwl[1:0]) control bits are used to select the length of the data words received by the sai. the data word length is defined by the number of serial clock cycles between two edges of the word select signal. word lengths of 16, 24, or 32 bits may be selected as shown in table 6-3 . the receive data registers are always loaded with 24 bits when a new data word arrives. if the 16-bit word length is selected, the received 16-bit data word will be placed in the 16 most significant bits of the receive data register, independent of the receiver data shift direction bit (rdir, see below), while the 8 least significant bits of the receive data register are cleared. if a 32-bit word length is selected, 8 bits are table 6-3 receiver word length control rwl1 rwl0 number of bits/word 00 16 01 24 10 32 1 1 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-12 dsp56004 user? manual motorola serial audio interface serial audio interface programming model discarded according to the receiver data word truncation (rdwt) control bit (see below). rwl[1:0] are also used to generate the word select indication when the receiver section is configured as master (rmst = 1). the rwl[1:0] bits are cleared during hardware reset and software reset. 6.3.2.6 rcs receiver data shift direction (rdir)?it 6 the read/write receiver data shift direction (rdir) control bit selects the shift direction of the received data. when rdir is cleared, receive data is shifted in most significant bit first. when rdir is set, the data is shifted in least significant bit first (see figure 6-5 ). the rdir bit is cleared during hardware reset and software reset. 6.3.2.7 rcs receiver left right selection (rlrs)?it 7 the read/write receiver left right selection (rlrs) control bit selects the polarity of the receiver word select (wsr) signal that identifies the left or right word in the input bit stream. when rlrs is cleared, wsr low identifies the left data word and wsr high identifies the right data word. when rlrs is set, wsr high identifies the left data word and wsr low identifies the right data word (see figure 6-6 ). the rlrs bit is cleared during hardware reset and software reset. figure 6-5 receiver data shift direction (rdir) programming figure 6-6 receiver left/right selection (rlrs) programming msb lsb lsb msb sdi sdi 12345678910111213141516 sckr rdir = 0 rdir = 1 aa0431 wsr left right rlrs = 1 wsr left right rlrs = 0 aa0432 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-13 6.3.2.8 rcs receiver clock polarity (rckp)?it 8 the read/write receiver clock polarity (rckp) control bit selects the polarity of the receiver serial clock. when rckp is cleared, the receiver clock polarity is negative. when rckp is set, the receiver clock polarity is positive. negative polarity means that the word select receive (wsr) and serial data in (sdix) lines change synchronously with the negative edge of the clock, and are considered valid during positive transitions of the clock. positive polarity means that the wsr and sdix lines change synchronously with the positive edge of the clock, and are considered valid during negative transitions of the clock (see figure 6-7 ). the rckp bit is cleared during hardware reset and software reset. 6.3.2.9 rcs receiver relative timing (rrel)?it 9 the read/write receiver relative timing (rrel) control bit selects the relative timing of the word select receive (wsr) signal as referred to the serial data input lines (sdix). when rrel is cleared, the transition of wsr, indicating start of a data word, occurs together with the first bit of that data word. when rrel is set, the transition of wsr occurs one serial clock cycle earlier (together with the last bit of the previous data word), as required by the i 2 s format (see figure 6-8 ). the rrel bit is cleared during hardware reset and software reset. figure 6-7 receiver clock polarity (rckp) programming sdi sckr rckp = 0 sdi sckr rckp = 1 wsr wsr aa0433 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-14 dsp56004 user? manual motorola serial audio interface serial audio interface programming model 6.3.2.10 rcs receiver data word truncation (rdwt)?it 10 the read/write receiver data word truncation (rdwt) control bit selects which 24-bit portion of a received 32-bit word will be transferred from the shift register to the data register. when rdwt is cleared, the first 24 bits received are transferred to the data register. when rdwt is set, the last 24 bits received are transferred to the data register. the rdwt bit is ignored if rwl[1:0] are set for a word length other than 32 bits (see figure 6-9 on page 6-14).the rdwt bit is cleared during hardware reset and software reset. figure 6-8 receiver relative timing (rrel) programming figure 6-9 receiver data word truncation (rdwt) programming msb lsb lsb msb sdi wsr msb left right msb lsb lsb msb sdi wsr msb left right lsb rrel = 0 rrel = 1 aa0434 sdi wsr sdi 12 4 6 8 101214161820222426283032 sckr left right rdwt = 0 rdwt = 1 12 4 6 8 101214161820222426283032 aa0435k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-15 6.3.2.11 rcs receiver interrupt enable (rxie)?it 11 when the read/write receiver interrupt enable (rxie) control bit is set, receiver interrupts for both left and right data words are enabled, and the dsp is interrupted if either the rldf or rrdf status bit is set. when rxie is cleared, receiver interrupts are disabled, however, rldf and rrdf bits still indicate the receive data register full conditions and can be polled for status. note that clearing rxie will mask a pending receiver interrupt only after a one-instruction-cycle delay. if rxie is cleared in a long interrupt service routine, it is recommended that at least one other instruction should be inserted between the instruction that clears rxie and the rti instruction at the end of the interrupt service routine. there are three different receive data interrupts that have separate interrupt vectors: 1. left channel receive interrupt is generated when rxie = 1, rldf = 1, and rrdf = 0. 2. right channel receive interrupt is generated when rxie = 1, rldf = 0, and rrdf = 1. 3. receive interrupt with exception (overrun) is generated when rxie = 1, rldf = 1, and rrdf = 1. this means that the previous data in the receive data register was lost and an overrun occurred. to clear rldf or rrdf during left or right channel interrupt service, the receive data registers of the enabled receivers must be read. clearing rldf or rrdf will clear the respective interrupt request. if the ?eceive interrupt with exception? indication is signaled (rldf = rrdf = 1) then rldf and rrdf are both cleared by reading the rcs register, followed by reading the receive data register of the enabled receivers. note: receivers 0 and 1 share the same controller. this means that the enabled receivers will be operating in parallel and any interrupt signaled will indicate a condition on all enabled receive data registers. the rxie bit is cleared during hardware reset and software reset. 6.3.2.12 rcs receiver interrupt location (rxil)?it 12 the read/write receiver interrupt location (rxil) control bit determines the location of the receiver interrupt vectors. when rxil = 0, the left channel receiver, the right channel receiver and the receiver exception interrupt vectors are located in program addresses $16, $18, and $1a, respectively. when rxil = 1, the left channel receiver, the right channel receiver and the receiver exception interrupt vectors are located in program addresses $46, $48, and $4a, respectively. the rxil bit is cleared during hardware reset and software reset. refer to table 6-1 on page 6-9. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-16 dsp56004 user? manual motorola serial audio interface serial audio interface programming model 6.3.2.13 rcs receiver left data full (rldf)?it 14 receiver left data full (rldf) is a read-only status bit that, together with rrdf (see below), indicates the status of the enabled receive data registers. rldf is set when the left data word (as indicated by wsr pin and the rlrs bit in the rcs) is transferred to the receive data registers after it was shifted in via the shift register of the enabled receiver. since audio data samples are composed of left and right data words that are read alternately, normal operation of the receivers occurs when either rldf or rrdf is set, in a corresponding alternating sequence. a receive overrun condition is indicated when both rldf and rrdf are set. rldf is cleared when the dsp reads the receive data register of the enabled receiver, provided that in case of a receive overrun condition, rldf is cleared by first reading the rcs, followed by reading the receive data register of the enabled receivers. rldf is also cleared by hardware and software reset, when the dsp is in the stop state, and when all receivers are disabled (r0en and r1en cleared). if rxie is set, an interrupt request will be issued when rldf is set. the vector of the interrupt request will depend on the state of the receive overrun condition. the rldf bit is cleared during hardware reset and software reset. 6.3.2.14 rcs receiver right data full (rrdf)?it 15 receiver right data full (rrdf) is a read-only status bit which, in conjunction with rldf, indicates the status of the enabled receive data register. rrdf is set when the right data word (as indicated by the wsr pin and the rlrs bit in rcs) is transferred to the receive data registers after being shifted in via the shift register of the enabled receiver. since audio data samples are composed of left and right data words that are read alternately, normal operation of the receivers occurs when either rldf or rrdf is set, in a corresponding alternating sequence. a receive overrun condition is indicated when both rldf and rrdf are set. rrdf is cleared when the dsp reads the receive data register of the enabled receiver, provided that in case of a receive overrun condition, rrdf is cleared by first reading the rcs, followed by reading the receive data register of the enabled receiver. rrdf is also cleared by hardware reset and software reset, when the dsp is in the stop state, and when all receivers are disabled (r0en and r1en cleared). if rxie is set, an interrupt request will be issued when rrdf is set. the vector of the interrupt request will depend on the state of the receive overrun condition. the rrdf bit is cleared during hardware reset and software reset. (rldf rrdf ? 1). = (rldf rrdf 1), = (rldf rrdf ? 1). = (rldf rrdf 1), = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-17 6.3.3 sai receive data registers (rx0 and rx1) the receive data registers (rx0 and rx1) are 24-bit read-only registers that accept data from the receive shift registers when all bits of the incoming data words have been received. the receive data registers alternately contain left-channel and right-channel data. the first data to appear in the data registers, after enabling operation of the respective receivers, will be the data for the left channel. 6.3.4 transmitter control/status register (tcs) the tcs is a 16-bit read/write control/status register used to direct the operation of the transmit section in the sai. the tcs register is shown in figure 6-4 on page 6-8. the control bits in the tcs determine the serial format of the data transfers. the status bits of the tcs are used by the dsp programmer to interrogate the status of the transmitter section. separate transmit enable and interrupt enable bits are also provided in the tcs. when read by the dsp, the tcs appears on the two low-order bytes of the 24-bit word, and the high-order byte is read as 0s. hardware reset and software reset clear all the bits in tcs. when the t0en, t1en, and t2en bits are cleared, the sai transmitter section is disabled and it enters the individual reset state after a one instruction cycle delay. while in the stop or individual reset state, the status bits in tcs are cleared. stop or individual reset do not affect the tcs control bits. the programmer should change tcs control bits (except for txie) only while the transmitter section is in the individual reset state, otherwise improper operation may result. the tcs bits are described in the following paragraphs. 6.3.4.1 tcs transmitter 0 enable (t0en)?it 0 the read/write control bit t0en enables the operation of the sai transmitter 0. when t0en is set, transmitter 0 is enabled. when t0en is cleared, transmitter 0 is disabled and the sdo0 line is set to high level. if t0en, t1en, and t2en are cleared, the sai transmitter section is disabled and enters the individual reset state. the t0en bit is cleared during hardware reset and software reset. 6.3.4.2 tcs transmitter 1 enable (t1en)?it 1 the read/write control bit t1en enables the operation of the sai transmitter 1. when t1en is set, transmitter 1 is enabled. when t1en is cleared, transmitter 1 is disabled and the sdo1 line is set to high level. if t0en, t1en and t2en are cleared, the sai transmitter section is disabled and enters the individual reset state. the t1en bit is cleared during hardware reset and software reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-18 dsp56004 user? manual motorola serial audio interface serial audio interface programming model 6.3.4.3 tcs transmitter 2 enable (t2en)?it 2 the read/write control bit t2en enables the operation of the sai transmitter 2. when t2en is set, transmitter 2 is enabled. when t2en is cleared, transmitter 2 is disabled and the sdo2 line is set to high level. if t0en, t1en, and t2en are cleared, the sai transmitter section is disabled and enters the individual reset state. the t2en bit is cleared during hardware reset and software reset. 6.3.4.4 tcs transmitter master (tmst)?it 3 the read/write control bit transmitter master ( tmst) determines whether the transmitter section operates in the master or slave mode. when tmst is set, the sai transmit section is configured as master. in the master mode the transmitter drives the sckt and wst pins. when tmst is cleared, the sai transmitter section is configured as a slave. in the slave mode, the sckt and wst pins are driven from an external source. the tmst bit is cleared during hardware reset and software reset. 6.3.4.5 tcs transmitter word length control (twl[1:0])?its 4 & 5 the read/write control bits transmitter word length (twl[1:0]) are used to select the length of the data words transmitted by the sai. the data word length is defined by the number of serial clock cycles between two edges of the word select signal. word lengths of 16, 24, or 32 bits may be selected as shown in table 6-4 . if the 16-bit word length is selected, the 16 msbs of the transmit data registers will be transmitted according to the data shift direction selected (see tdir bit, below). if 32-bit word length is selected, the 24-bit data word from the transmit data register is expanded to 32 bits according to the tdwe control bit (see tdwe, below). twl[1:0] are also used to generate the word select indication when the transmitter is configured as master (tmst = 1). the twl[1:0] bits are cleared during hardware reset and software reset. 6.3.4.6 tcs transmitter data shift direction (tdir)?it 6 the read/write transmitter data shift direction (tdir) control bit selects the shift direction of the transmitted data. when tdir is cleared, transmit data is shifted out msb first. when tdir is set, the data is shifted out lsb first (see figure 6-10 ). the tdir bit is cleared during hardware reset and software reset. table 6-4 transmitter word length twl1 twl0 number of bits per word 00 16 01 24 10 32 1 1 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-19 6.3.4.7 tcs transmitter left right selection (tlrs)?it 7 the read/write transmitter left right selection (tlrs) control bit switches the polarity of the word select transmit (wst) signal that identifies the left or right word in the output bit stream. when tlrs is cleared, wst low identifies the left data word and wst high identifies the right data word. when tlrs is set, wst high identifies the left data word and wst low identifies the right data word (see figure 6-11 ). the tlrs bit is cleared during hardware reset and software reset. 6.3.4.8 tcs transmitter clock polarity (tckp)?it 8 the read/write transmitter clock polarity (tckp) control bit switches the polarity of the transmitter serial clock. when tckp is cleared, the transmitter clock polarity is negative. negative polarity means that the word select transmit (wst) and serial data out (sdox) lines change synchronously with the negative edge of the clock, and are considered valid during positive transitions of the clock. when tckp is set, the transmitter clock polarity is positive. positive polarity means that the wst and sdox lines change synchronously with the positive edge of the clock, and are considered valid during negative transitions of the clock (see figure 6-12 ). the tckp bit is cleared during hardware reset and software reset. figure 6-10 transmitter data shift direction (tdir) programming figure 6-11 transmitter left/right selection (tlrs) programming msb lsb lsb msb sdo sdo 12345678910111213141516 sckt tdir = 0 tdir = 1 aa0436k wst left right tlrs = 1 wst left right tlrs = 0 aa0437k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-20 dsp56004 user? manual motorola serial audio interface serial audio interface programming model 6.3.4.9 tcs transmitter relative timing (trel)?it 9 the read/write transmitter relative timing (trel) control bit selects the relative timing of the wst signal as referred to the serial data output lines (sdox). when trel is cleared, the transition of wst, indicating the start of a data word, occurs together with the first bit of that data word. when trel is set, the transition of wst occurs one serial clock cycle earlier (together with the last bit of the previous data word), as required by the i 2 s format (see figure 6-13 ).the trel bit is cleared during hardware reset and software reset. 6.3.4.10 tcs transmitter data word expansion (tdwe)?it 10 the read/write transmitter data word expansion (tdwe) control bit selects the method used to expand a 24-bit data word to 32 bits during transmission. when tdwe is cleared, after transmitting the 24-bit data word from the transmit data figure 6-12 transmitter clock polarity (tckp) programming figure 6-13 transmitter relative timing (trel) programming sdo sckt tckp = 0 sdo sckt tckp = 1 wst wst aa0438k msb lsb lsb msb sdo wst msb left right msb lsb lsb msb sdo wst msb left right lsb trel = 0 trel = 1 aa0439 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-21 register, the last bit is transmitted eight times. when tdwe is set, the first bit is transmitted 8 times and then the 24-bit data word from the transmit data register is transmitted. the tdwe bit is ignored if twl[1:0] are set for a word length other than 32 bits (see figure 6-14 ). the tdwe bit is cleared during hardware reset and software reset. 6.3.4.11 tcs transmitter interrupt enable (txie)?it 11 when the read/write transmitter interrupt enable (txie) control bit is set, transmitter interrupts for both left and right data words are enabled, and the dsp is interrupted if either the tlde or trde status bit is set. when txie is cleared, transmitter interrupts are disabled. however, the tlde and trde bits still signal the transmit data register empty conditions. clearing txie will mask a pending transmitter interrupt only after a one-instruction-cycle delay. if txie is cleared in a long interrupt service routine, it is recommended that at least one other instruction should be inserted between the instruction that clears txie and the rti instruction at the end of the interrupt service routine. there are three different transmit data interrupts that have separate interrupt vectors: 1. left channel transmit interrupt is generated when txie = 1, tlde = 1, and trde = 0. the transmit data registers should be loaded with the left data words. 2. right channel transmit interrupt is generated when txie = 1, tlde = 0, and trde = 1. the transmit data registers should be loaded with the right data words. 3. transmit interrupt with exception (underrun) is generated when txie = 1, tlde = 1, and trde = 1. this means that old data is being retransmitted. figure 6-14 transmitter data word expansion (tdwe) programming sdi wst sdo 12 4 6 8 101214161820222426283032 sckt left right tdwe = 0 tdwe = 1 12 4 6 8 101214161820222426283032 aa0440k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-22 dsp56004 user? manual motorola serial audio interface serial audio interface programming model to clear tlde or trde during left or right channel interrupt service, the transmit data registers of the enabled transmitters must be written. clearing tlde or trde will clear the respective interrupt request. if the ?ransmit interrupt with exception? indication is signaled (tlde = trde = 1) then tlde and trde are both cleared by reading the tcs register, followed by writing to the transmit data register of the enabled transmitters. note: transmitters 0, 1, and 2 share the same controller. this means that the enabled transmitters will be operating in parallel and any interrupt that is signaled will indicate a condition on all enabled transmit data registers. the txie bit is cleared during hardware reset and software reset. 6.3.4.12 tcs transmitter interrupt location (txil)?it 12 the read/write transmitter interrupt location (txil) control bit selects the location of the transmitter interrupt vectors. when txil = 0, the left channel transmitter, the right channel transmitter, and the transmitter exception interrupt vectors are located in program addresses $10, $12, and $14, respectively. when txil = 1, the left channel transmitter, the right channel transmitter, and the transmitter exception interrupt vectors are located in program addresses $40, $42, and $44, respectively. the txil bit is cleared during hardware reset and software reset. refer to table 6-1 on page 6-9. 6.3.4.13 tcs reserved bit?it 13 bit 13 in tcs is reserved and unused. it is read as 0s and should be written with 0 for future compatibility. 6.3.4.14 tcs transmitter left data empty (tlde)?it 14 transmitter left data empty (tlde) is a read-only status bit that, in conjunction with trde, indicates the status of the enabled transmit data registers. tlde is set when the right data words (as indicated by the tlrs bit in tcs) are simultaneously transferred from the transmit data registers to the transmit shift registers in the enabled transmitters. this means that the transmit data registers are now free to be loaded with the left data words. since audio data samples are composed of left and right data words that are transmitted alternately, normal operation of the transmitters is achieved when only one of the status bits (tlde or trde) is set at a time. a transmit underrun condition is indicated when both tlde and trde are set. tlde is cleared when the dsp writes to the transmit data registers of the enabled transmitters, provided that when a transmit underrun condition occurs, the previous data (which is still present in the data registers) will be re-transmitted. in this case, tlde is cleared by first reading the tcs register, followed by writing the transmit data registers of the enabled transmitters. if txie is set, an interrupt request will be issued when tlde is set. the vector of the interrupt request will depend on the state of the transmit underrun (tlde trde ? 1). = (tlde trde 1), = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface serial audio interface programming model motorola dsp56004 user? manual 6-23 condition. tlde is cleared by hardware reset and software reset, when the dsp is in the stop state, and when all transmitters are disabled (t2en, t1en, and t0en cleared). 6.3.4.15 tcs transmitter right data empty (trde)?it 15 transmitter right data empty (trde) is a read-only status bit that, in conjunction with tlde, indicates the status of the enabled transmit data registers. trde is set when the left data words (as indicated by the tlrs bit in tcs) are simultaneously transferred from the transmit data registers to the transmit shift registers in the enabled transmitters. this indicates that the transmit data registers are now free to be loaded with the right data words. since audio data samples are composed of left and right data words that are transmitted alternately, normal operation of the transmitters is achieved when only one of the status bits (tlde or trde) is set at a time. a transmit underrun condition is indicated when both tlde and trde are set. trde is cleared when the dsp writes to the transmit data register of the enabled transmitters, provided that when a transmit underrun condition occurs, the previous data (which is still present in the data registers) will be re-transmitted. in this case, trde is cleared by first reading the tcs register, followed by writing the transmit data registers of the enabled transmitters. if txie is set, an interrupt request will be issued when trde is set. the vector of the interrupt request will depend on the state of the transmit underrun condition. the trde is cleared by hardware and software reset, when the dsp is in the stop state, and when all transmitters are disabled (t2en, t1en and t0en cleared). 6.3.5 sai transmit data registers (tx2, tx1 and tx0) the three transmit data registers (tx2, tx1, and tx0) are each 24 bits wide. data to be transmitted is written to these registers and is automatically transferred to the associated shift register after the last bit is shifted out. the transmit data registers should be written with left channel and right channel data alternately. the first word to be transmitted, after enabling the operation of the respective transmitter, will be the left channel word. (tlde trde ? 1). = (tlde trde 1), = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-24 dsp56004 user? manual motorola serial audio interface programming considerations 6.4 programming considerations this section discusses some important considerations for programming the sai. 6.4.1 sai operation during stop the sai operation cannot continue when the dsp is in the stop state, since no dsp clocks are active. incoming serial data will be ignored. while the dsp is in the stop state, the sai sections will remain in the individual reset state and the status bits in the rcs and tcs registers will be cleared. no control bits in the rcs and tcs registers are affected. it is recommended that the sai be disabled before entering the stop state. 6.4.2 initiating a transmit session the recommended method of initializing a transmit session is to first write valid data to the transmit data registers and then enable the transmit operation. this will ensure that known data will be transmitted as soon as the transmitters are enabled (if operating in the master mode), or as soon as the word select event for the left word is detected on the wst pin (if operating in the slave mode). note that even though the trde and tlde status flags are always cleared while the transmitter section is in the individual reset state, the transmit data registers may be written in this state. the data will remain in the transmit data registers while the transmitter section is in the individual reset state, and will be transferred to the transmit shift registers only after the respective transmitters are enabled and when the left word transmission slot occurs (immediately for master mode, or according to wst for slave mode). 6.4.3 using a single interrupt to service both receiver and transmitter sections it is possible to use a single interrupt routine to service both the receiver and transmitter sections if both sections are fully synchronized. to ensure full synchronization, both sections must operate with the same protocol and the same clock source. only the receive interrupts (rxie = 1) should be enabled for proper operation in this configuration. when the condition arises for the receive interrupt to occur, the same interrupt service routine may be used to read data from the receiver section and to write data to the transmitter section. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial audio interface programming considerations motorola dsp56004 user? manual 6-25 when operating in the master mode, the following initialization procedure is recommended: 1. write the left data words to the transmit data registers. 2. enable the operation of the sai receivers while ensuring that rxie = 1 (rcs register). 3. enable the operation of the sai transmitters while ensuring that txie = 0 (tcs register). enabling the transmitters will transfer the left data words from the transmit data registers to the shift registers. 4. poll the trde status bit in the tcs register to detect when it is possible to load the right data words into the transmit data registers. write the right data words to the transmit data registers when trde is set. 5. from now on, the receive interrupts should be used to service both the transmitters and receivers. when the left channel receive interrupt is generated, the interrupt service routine should write the left data words to the transmitters and read the received left data words from the receivers (repeat this methodology for the right channel receivers/transmitters). 6.4.4 sai state machine when the sai operates in the slave mode and the bit clock and word select inputs change unexpectedly, irregular or unexpected operation might result. in particular, this can happen when sckr (sckt) runs freely and wsr/wst transitions occur earlier or later than expected (in terms of complete bit clock cycles). in order to explore the sai reaction in such irregular conditions, the operation of the sai state machine is described here. after completion of a data word transfer (or upon exiting the individual reset state) the sai searches for the particular wsr/wst transition with regard to the left/right orientation of the next expected word. for example, after completion of a right data word transfer or upon exiting the individual reset state, the sai searches for a wsr/wst transition, which determines the start of a left data word transfer. similarly, after completion of a left data word transfer, the sai searches for a wsr/wst transition, which determines the start of a right data word transfer. as soon as the correct transition is detected the sai begins to shift the data in (receive) or out (transmit) one shift per bit-clock cycle. a data word transfer is complete when the number of the incoming bit clocks in sckr (sckt) since the detection of the correct wsr/wst transition reaches the value of the pre-programmed data word length. during a data word transfer (i.e., before completion), all transitions in wsr/wst are ignored. after completion of a data word transfer the sai stops shifting data in and out until the next correct wsr/wst transition is detected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-26 dsp56004 user? manual motorola serial audio interface programming considerations as a result, when the wsr/wst transition appears earlier than expected, the transition is ignored and the next pair of data words (right and left) is lost. likewise, when the wsr/wst transition appears later than expected, in the time period between the completion of the previous word and the appearance of the late wsr/wst transition, the data bits being received are ignored and no data is transmitted. these characteristics can be used to disable reception or transmission of undesired data words by keeping sckr (sckt) running freely and gating wsr/wst for a certain number of bit-clock cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual 7-1 section 7 general purpose input/output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-2 dsp56004 user? manual motorola general purpose input/output 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 gpio programming model . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 gpio register (gpior) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose input/output introduction motorola dsp56004 user? manual 7-3 7.1 introduction the general purpose input/output (gpio) pins are used for control and handshake functions between the dsp and external circuitry. the gpio port has four i/o signals (gpio0?pio3) that are controlled through a memory-mapped register. each gpio signal may be individually programmed as an output or as an input. 7.2 gpio programming model the gpio pins are controlled through the gpio control/data register (gpior), which is illustrated in figure 7-1 . the register is described in the following paragraphs. 7.3 gpio register (gpior) the gpio register (gpior) is a 24-bit read/write control/data register used to operate and configure the gpio pins. the control bits in the gpior select the direction of data transfer for each pin, whereas the data bits in the gpior are used to read from or write to the gpio pins. hardware reset and software reset clear all the bits in gpior. the gpior bits are described in the following paragraphs. figure 7-1 gpio control/data register gd0 0 gpior reserved bit x:$fff7 gd1 1 gd2 2 gd3 3 4 5 6 7 gdd0 8 gdd1 9 gdd2 10 gdd3 11 12 13 14 15 gc0 16 gc1 17 gc2 18 gc3 19 20 21 22 23 aa0441 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-4 dsp56004 user? manual motorola general purpose input/output gpio register (gpior) 7.3.1 gpior data bits (gd[3:0])?its 3? the read/write gpio data bits (gd[3:0]) are used to read from or write to the corresponding gpio[3:0] pins. if the gpiox pin is defined as an input, the gdx bit will reflect the logic value present on the gpiox pin. if the gpiox pin is defined as an output, the gpiox pin will reflect the value written to the gdx bit. the gd[3:0] bits are cleared during hardware reset and software reset. 7.3.2 gpior reserved bits?its 4?, 12?5, and 20?3 these bits are reserved and unused. they read as 0s and should be written with 0s for future compatibility. 7.3.3 gpior data direction bits (gdd[3:0])?its 11? the read/write gpio data direction bits (gdd[3:0]) select the direction of data transfer for each of the gpio[3:0] pins (see table 7-1 ). when the gddx bit is cleared, the corresponding gpiox pin is defined as an input. when the gddx bit is set, the corresponding gpiox pin is defined as an output. the gdd[3:0] bits are cleared during hardware reset and software reset. 7.3.4 gpior control bits (gc[3:0])?its 19?6 the read/write gpio control bits (gc[3:0]) select the type of output buffer for each of the gpio[3:0] pins when the pins are defined as outputs, and select whether or not the input buffer is connected to the pin when the pin is defined as an input. table 7-1 gpio pin configuration gddx gcx gpio pin definition 0 0 disconnected 0 1 input 1 0 standard active high/active low output 1 1 open-drain output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose input/output gpio register (gpior) motorola dsp56004 user? manual 7-5 when the gcx bit is cleared and the gddx bit is cleared (the pin is defined as an input), the corresponding gpiox pin input buffer is disconnected from the pin and does not require an external pull-up (see table 7-1 and figure 7-2 ). when the gcx bit is set and the gddx bit is cleared (the pin is defined as input), the corresponding gpiox pin input buffer is connected to the pin (see table 7-1 and figure 7-2 ). when the gcx bit is cleared and the gddx bit is set (the pin is defined as output), the corresponding gpiox pin output buffer is defined as a standard active high/active low type (see table 7-1 and figure 7-2 ). when the gcx bit is set and the gddx bit is set (the pin is defined as output), the corresponding gpiox pin output buffer is defined as an open-drain type (see table 7-1 and figure 7-2 ). the gc[3:0] bits are cleared during hardware reset and software reset. figure 7-2 gpio circuit diagram gd0-gd3 pin gdd gdd gc * see table 7-1 gpio pin configuration . buffer control* gdd aa0442k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-6 dsp56004 user? manual motorola general purpose input/output gpio register (gpior) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual a-1 appendix a bootstrap rom and data rom contents 10 0 0 01 1 01 10 10 0 0 01 1 01 10 10 0 0 01 1 01 10 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 10 0 0 01 1 01 10 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-2 dsp56004 user? manual motorola bootstrap rom and data rom contents a.1 dsp56004 bootstrap program. . . . . . . . . . . . . . . . . . a-3 a.2 dsp56004rom bootstrap program . . . . . . . . . . . . . a-5 a.3 assembler code to generate x data rom . . . . . . a-7 a.4 log2 x table (x data rom) . . . . . . . . . . . . . . . . . . . . . . a-8 a.5 2x table (x data rom) . . . . . . . . . . . . . . . . . . . . . . . . . a-10 a.6 sine wave table (y data rom). . . . . . . . . . . . . . . . . . a-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap rom and data rom contents motorola dsp56004 user? manual a-3 a.1 dsp56004 bootstrap program ; bootstrap code for dsp56004 - (c) copyright 1991 motorola inc. ; revised january 21, 1992. ; ; bootstrap through the shi and emi. ; ; assumes 32 words of bootstrap rom in the address range p:$0-p:$1f plus ; 32 words of bootstrap rom in the address range p:$100-p:$11f. ; ; all bootstrap modes will clear (write a $000000 word) the internal ; x, y and p rams. ; bcr equ $fffe ; bcr register ogdbr equ $fffc ; once gdb register gpior equ $fff7 ; gpio control/data register gdd3 equ 11 ; direction bit for gpio3 gd3 equ 3 ; data bit for gpio3 ecsr equ $ffeb ; emi control/status register edrr0 equ $ffea ; emi data read register ebar0 equ $ffe8 ; emi base address register 0 eor0 equ $ffe9 ; emi offset register edrf equ 13 ; emi edrr full flag hrne equ 17 ; shi fifo not empty flag hrx equ $fff3 ; shi hrx fifo hcsr equ $fff1 ; shi control/status register hi2c equ 1 ; shi iic enable control bit ma equ 0 ; omr mode a mb equ 1 ; omr mode b mc equ 4 ; omr mode c org pl:$0,pl:$0 ; bootstrap code starts at $0 start clr a #<0,r0 movep a,x:bcr ; clear bcr register rep #256 ; clear x and y data rams move a,l:(r0)+ move #<0,r0 rep #512 ; clear program ram move a,p:(r0)+ jset #mc,omr,shild ; if mc:mb:ma=1xx, go load from shi ; this is the routine that loads from external eprom. ; if mc:mb:ma=001, the internal pram is loaded with 1,536 consecutive ; bytes from an eprom connected to the emi. the eprom is located at the emi ; address $0, when operating the emi in the absolute addressing sram mode ; (eam2-eam0=000). it is assumed that the eprom is selected (enabled) through ; the gpio3 pin, which is driven low by this bootstrap mode. the gpio3 output ; is programmed to be of the active high/active low type. the bytes will be ; condensed into 512 24-bit words and stored in contiguous pram memory locations ; starting at p:$0. note that the routine loads data starting with the least ; significant byte of p:$0. the once is enabled by the emi bootstrap. epromld movep a,x:ogdbr ; enable the once move #<0,r0 ; start loading code at p:$0 movep a,x:ebar0 ; eprom starting address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-4 dsp56004 user? manual motorola bootstrap rom and data rom contents movep #$fc0085,x:ecsr ; emi control ; ebw=1, ewl1-ewl0=10, eam2-eam0=000, einr=1, einw=0, eis1-eis0=00, ; erts=0, etdm=1, estm3-estm0=1111, eme=1 bset #gdd3,x:gpior ; enable eprom (gpio3=0) ; gd3-gd0=0000, gdd3-gdd0=1000,gc3-gc0=0000 do #512,_loop1 movep a,x:eor0 ; trigger read jclr #edrf,x:ecsr,* ; wait for edrr full movep x:edrr0,p:(r0)+ ; store in program ram _loop1 bset #gd3,x:gpior ; disable eprom (gpio3=1) ; gd3-gd0=1000, gdd3-gdd0=1000,gc3-gc0=0000 ; exit bootstrap rom exit andi #$ec,omr ; set operating mode to 0 (and trigger an exit from ;bootstrap mode). nop ; delay needed for op. mode change jmp <$0 ; then go to loaded program. ; this is the routine that loads from the serial host interface. ; mc:mb:ma=101 - bootstrap from shi (spi) ; mc:mb:ma=111 - bootstrap from shi (iic) ; if mc:mb:ma=1x1, the internal pram is loaded with 512 words received ; through the serial host interface (shi). the shi operates in the slave ; mode, with the 10-word fifo enabled, and with the hreq pin enabled for ; receive operation. the word size for transfer is 24 bits. the shi ; operates in the spi or in the iic mode, according to the bootstrap ; mode. the once is enabled by the bootstrap code. shild jclr #ma,omr,ma_0 shild_1 movep a,x:ogdbr ; enable the once move #$0002a9,x1 ; shi control word (spi) ; hen=1, hi2c=0, hm1-hm0=10, hfifo=1, hmst=0, ; hrqe1-hrqe0=01, hidle=1, hbie=0, htie=0, hrie1-hrie0=00 move #<0,r0 ; start loading code at p:$0 jmp <$100 org pl:$100,pl:$100 ; start of second 32-word group jclr #mb,omr,shi_loop ; if mc:mb:ma=101, then spi bset #hi2c,x1 ; iic (hi2c=1) shi_loop movep x1,x:hcsr ; enable shi do #512,_loop2 jclr #hrne,x:hcsr,* ; wait for hrx not empty movep x:hrx,p:(r0)+ ; store in program ram _loop2 jmp a-6 dsp56004 user? manual motorola bootstrap rom and data rom contents ; the gpio3 pin, which is driven low by this bootstrap mode. the gpio3 output ; is programmed to be of the active high/active low type. the bytes will be ; condensed into 256 24-bit words and stored in contiguous pram memory locations ; starting at p:$0. note that the routine loads data starting with the least ; significant byte of p:$0. epromld movep #$fc0085,x:ecsr ; emi control ; ebw=1, ewl1-ewl0=10, eam2-eam0=000, einr=1, einw=0, eis1-eis0=00, ; erts=0, etdm=1, estm3-estm0=1111, eme=1 bset #gdd3,x:gpior ; enable eprom (gpio3=0) ; gd3-gd0=0000, gdd3-gdd0=1000,gc3-gc0=0000 do #256,_loop1 movep a1,x:eor0 ; trigger read jclr #edrf,x:ecsr,* ; wait for edrr full movep x:edrr0,p:(r0)+ ; store in program ram _loop1 bset #gd3,x:gpior ; disable eprom (gpio3=1) ; gd3-gd0=1000, gdd3-gdd0=1000,gc3-gc0=0000 jmp a-8 dsp56004 user? manual motorola bootstrap rom and data rom contents a.4 log 2 x table (x data rom) _org x: $0100 l2_00 dc $800000 ;-1.0000000 l2_01 dc $816fe5 ;-0.9887727 l2_02 dc $82dcf3 ;-0.9776322 l2_03 dc $844734 ;-0.9665771 l2_04 dc $85aeb5 ;-0.9556059 l2_05 dc $87137f ;-0.9447175 l2_06 dc $88759c ;-0.9339108 l2_07 dc $89d518 ;-0.9231844 l2-08 dc $8b31fb ;-0.9125372 l2-09 dc $8c8c51 ;-0.9019679 l2-0a dc $8de421 ;-0.8914756 l2_0b dc $8f3976 ;-0.8810589 l2_0c dc $908c59 ;-0.8707169 l2_0d dc $91dcd2 ;-0.8604486 l2_0e dc $932aea ;-0.8502529 l2_0f dc $9476aa ;-0.8401287 l2_10 dc $95c01a ;-0.8300750 l2_11 dc $970743 ;-0.8200909 l2_12 dc $984c2c ;-0.8101754 l2_13 dc $98edd ;-0.8003277 l2_14 dc $9acf5e ;-0.7905467 l2_15 dc $9c0db7 ;-0.7808315 l2_16 dc $9d49ee ;-0.7711813 l2_17 dc $9e840c ;-0.7615952 l2_18 dc $9fbc17 ;-0.7520725 l2_19 dc $a0f216 ;-0.7426121 l2_1a dc $a22610 ;-0.7332134 l2_1b dc $a3580b ;-0.7238756 l2_1c dc $a4880f ;-0.7145978 l2_1d dc $a5b622 ;-0.7053792 l2_1e dc $a6e24a ;-0.6962192 l2_1f dc $a80c8c ;-0.6871171 l2_20 dc $a934f1 ;-0.6780719 l2_21 dc $aa5b7c ;-0.6690831 l2_22 dc $ab8034 ;-0.6601501 l2_23 dc $aca320 ;-0.6512718 l2_24 dc $adc444 ;-0.6424479 l2_25 dc $aee3a5 ;-0.6336778 l2_26 dc $b0014b ;-0.6249605 l2_27 dc $b11d39 ;-0.6162957 l2_28 dc $b23775 ;-0.6076826 l2_29 dc $b35004 ;-0.5991206 l2_2a dc $b466ec ;-0.5906091 l2_2b dc $b57c31 ;-0.5821475 l2_2c dc $b68fd8 ;-0.5737352 l2_2d dc $b7a1e6 ;-0.5653718 l2_2e dc $b8b25f ;-0.5570565 l2_2f dc $b9c149 ;-0.5487889 l2_30 dc $bacea8 ;-0.5405684 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap rom and data rom contents motorola dsp56004 user? manual a-9 l2_31 dc $bbda80 ;-0.5323944 l2_32 dc $bce4d5 ;-0.5242666 l2_33 dc $bdedad ;-0.5161842 l2_34 dc $bef50b ;-0.5081469 l2_35 dc $bffaf3 ;-0.5001541 l2_36 dc $c0ff6a ;-0.4922054 l2_37 dc $c20274 ;-0.4843001 l2_38 dc $c30414 ;-0.4764380 l2_39 dc $c4044f ;-0.4686185 l2_3a dc $c50328 ;-0.4608412 l2_3b dc $c600a3 ;-0.4531056 l2_3c dc $c6fcc4 ;-0.4454112 l2_3d dc $c7f78f ;-0.4377576 l2_3e dc $c8f107 ;-0.4301444 l2_3f dc $c9e930 ;-0.4225712 l2_40 dc $cae00d ;-0.4150375 l2_41 dc $cbd5a2 ;-0.4075429 l2_42 dc $ccc9f2 ;-0.4000871 l2_43 dc $cdbd00 ;-0.3926697 l2_44 dc $ceaed0 ;-0.3852901 l2_45 dc $cf9f65 ;-0.3779482 l2_46 dc $d08ec2 ;-0.3706434 l2_47 dc $d17cea ;-0.3633754 l2_48 dc $d269e1 ;-0.3561438 l2_49 dc $d355a9 ;-0.3489484 l2_4a dc $d44046 ;-0.3417885 l2_4b dc $d529ba ;-0.3346641 l2_4c dc $d61209 ;-0.3275746 l2_4d dc $d6f934 ;-0.3205199 l2_4e dc $d7df40 ;-0.3134995 l2_4f dc $d8c42e ;-0.3065131 l2_50 dc $d9a802 ;-0.2995603 l2_51 dc $da8abe ;-0.2926409 l2_52 dc $db6c66 ;-0.2857544 l2_53 dc $dc4cfa ;-0.2789009 l2_54 dc $dd2c7f ;-0.2720796 l2_55 dc $de0af7 ;-0.2652904 l2_56 dc $dee864 ;-0.2585330 l2_57 dc $dfc4c9 ;-0.2518071 l2_58 dc $e0a027 ;-0.2451125 l2_59 dc $e17a83 ;-0.2384487 l2_5a dc $e253dd ;-0.2318157 l2_5b dc $e32c39 ;-0.2252129 l2_5c dc $e40398 ;-0.2186403 l2_5d dc $e4d9fe ;-0.2120974 l2_5e dc $e5af6b ;-0.2055842 l2_5f dc $e683e3 ;-0.1991001 l2_60 dc $e75768 ;-0.1926451 l2_61 dc $e829fb ;-0.1862189 l2_62 dc $e8fba0 ;-0.1798210 l2_63 dc $e9cc57 ;-0.1734515 l2_64 dc $ea9c24 ;-0.1671100 l2_65 dc $eb6b08 ;-0.1607962 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-10 dsp56004 user? manual motorola bootstrap rom and data rom contents l2_66 dc $ec3905 ;-0.1545099 l2_67 dc $ed061d ;-0.1482509 l2_68 dc $edd252 ;-0.1420190 l2_69 dc $ee9da7 ;-0.1358138 l2_6a dc $ef681c ;-0.1296353 l2_6b dc $f031b5 ;-0.1234831 l2_6c dc $f0fa73 ;-0.1173569 l2_6d dc $f1c257 ;-0.1112567 l2_6e dc $f28963 ;-0.1051823 l2_6f dc $f34f9b ;-0.0991331 l2_70 dc $f414fe ;-0.0931094 l2_71 dc $f4d98f ;-0.0871106 l2_72 dc $f59d50 ;-0.0811367 l2_73 dc $f66042 ;-0.0751874 l2_74 dc $f72267 ;-0.0692626 l2_75 dc $f7e3c1 ;-0.0633620 l2_76 dc $f8a451 ;-0.0574855 l2_77 dc $f96419 ;-0.0516328 l2_78 dc $fa231b ;-0.0458037 l2_79 dc $fae158 ;-0.0399981 l2_7a dc $fb9ed2 ;-0.0342157 l2_7b dc $fc5b8a ;-0.0284564 l2_7c dc $fd1782 ;-0.0227201 l2_7d dc $fdd2bc ;-0.0170064 l2_7e dc $fe8d38 ;-0.0113153 l2_7f dc $ff46f9 ;-0.0056466 a.5 2 x table (x data rom) _data x 0180 al2_00 dc $400000 ;+0.5000000 al2_01 dc $4058f7 ;+0.5027150 al2_02 dc $40b269 ;+0.5054446 al2_03 dc $410c58 ;+0.5081892 al2_04 dc $4166c3 ;+0.5109485 al2_05 dc $41c1ad ;+0.5137230 al2_06 dc $421d14 ;+0.5165124 al2_07 dc $4278fb ;+0.5193170 al2_08 dc $42d562 ;+0.5221369 al2_09 dc $433249 ;+0.5249721 al2_0a dc $438fb1 ;+0.5278226 al2_0b dc $43ed9b ;+0.5306886 al2_0c dc $444c07 ;+0.5335702 al2_0d dc $44aaf7 ;+0.5364674 al2_0e dc $450a6b ;+0.5393804 al2_0f dc $456a63 ;+0.5423092 al2_10 dc $45cae1 ;+0.5452539 al2_11 dc $462be5 ;+0.5482146 al2_12 dc $468d70 ;+0.5511913 al2_13 dc $46ef82 ;+0.5541842 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap rom and data rom contents motorola dsp56004 user? manual a-11 al2_14 dc $47521d ;+0.5571934 al2_15 dc $47b541 ;+0.5602189 al2_16 dc $4818ee ;+0.5632608 al2_17 dc $487d26 ;+0.5663192 al2_18 dc $48e1ea ;+0.5693944 al2_19 dc $494739 ;+0.5724860 al2_1a dc $49ad16 ;+0.5755947 al2_1b dc $4a1380 ;+0.5787201 al2_1c dc $4a7a78 ;+0.5818624 al2_1d dc $4ae1ff ;+0.5850219 al2_1e dc $4b4a17 ;+0.5881985 al2_1f dc $4bb2bf ;+0.5913924 al2_20 dc $4c1bf8 ;+0.5946035 al2_21 dc $4c85c4 ;+0.5978322 al2_22 dc $4cf023 ;+0.6010784 al2_23 dc $4d5b15 ;+0.6043421 al2_24 dc $4dc69d ;+0.6076237 al2_25 dc $4e32ba ;+0.6109231 al2_26 dc $4e9f6d ;+0.6142403 al2_27 dc $4f0cb7 ;+0.6175755 al2_28 dc $4f7a99 ;+0.6209289 al2_29 dc $4fe914 ;+0.6243005 al2_2a dc $505829 ;+0.6276904 al2_2b dc $50c7d7 ;+0.6310986 al2_2c dc $513822 ;+0.6345255 al2_2d dc $51a908 ;+0.6379709 al2_2e dc $521a8b ;+0.6414350 al2_2f dc $528cac ;+0.6449180 al2_30 dc $52ff6b ;+0.6484197 al2_31 dc $5372ca ;+0.6519406 al2_32 dc $53e6ca ;+0.6554806 al2_33 dc $545b6b ;+0.6590399 al2_34 dc $54d0ad ;+0.6626183 al2_35 dc $554693 ;+0.6662163 al2_36 dc $55bd1d ;+0.6698338 al2_37 dc $56344b ;+0.6734709 al2_38 dc $56ac1f ;+0.6771277 al2_39 dc $57249a ;+0.6808045 al2_3a dc $579dbc ;+0.6845012 al2_3b dc $581787 ;+0.6882180 al2_3c dc $5891fb ;+0.6919550 al2_3d dc $590d19 ;+0.6957122 al2_3e dc $5988e2 ;+0.6994898 al2_3f dc $5a0557 ;+0.7032880 al2_40 dc $5a827a ;+0.7071068 al2_41 dc $5b004a ;+0.7109463 al2_42 dc $5b7ec9 ;+0.7148067 al2_43 dc $5bfdf8 ;+0.7186880 al2_44 dc $5c7dd8 ;+0.7225904 al2_45 dc $5cfe69 ;+0.7265140 al2_46 dc $5d7fad ;+0.7304589 al2_47 dc $5e01a5 ;+0.7344252 al2_48 dc $5e8452 ;+0.7384131 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-12 dsp56004 user? manual motorola bootstrap rom and data rom contents al2_49 dc $5f07b4 ;+0.7424226 al2_4a dc $5f8bcd ;+0.7464539 al2_4b dc $60109d ;+0.7505070 al2_4c dc $609626 ;+0.7545822 al2_4d dc $611c69 ;+0.7586795 al2_4e dc $61a366 ;+0.7627990 al2_4f dc $622b1f ;+0.7669410 al2_50 dc $62b395 ;+0.7711054 al2_51 dc $633cc8 ;+0.7752924 al2_52 dc $63c6ba ;+0.7795022 al2_53 dc $64516c ;+0.7837348 al2_54 dc $64dcdf ;+0.7879905 al2_55 dc $656913 ;+0.7922691 al2_56 dc $65f60a ;+0.7965710 al2_57 dc $6683c6 ;+0.8008964 al2_58 dc $671246 ;+0.8052452 al2_59 dc $67a18c ;+0.8096175 al2_5a dc $68319a ;+0.8140137 al2_5b dc $68c270 ;+0.8184338 al2_5c dc $69540f ;+0.8228778 al2_5d dc $69e678 ;+0.8273458 al2_5e dc $6a79ad ;+0.8318383 al2_5f dc $6b0daf ;+0.8363551 al2_60 dc $6ba27e ;+0.8408964 al2_61 dc $6c381d ;+0.8454624 al2_62 dc $6cce8b ;+0.8500532 al2_63 dc $6d65ca ;+0.8546689 al2_64 dc $6dfddc ;+0.8593097 al2_65 dc $6e96c1 ;+0.8639756 al2_66 dc $6f307a ;+0.8686669 al2_67 dc $6fcb09 ;+0.8733836 al2_68 dc $70666f ;+0.8781260 al2_69 dc $7102ad ;+0.8828942 al2_6a dc $719fc5 ;+0.8876883 al2_6b dc $723db6 ;+0.8925083 al2_6c dc $72dc83 ;+0.8973545 al2_6d dc $737c2d ;+0.9022270 al2_6e dc $741cb5 ;+0.9071261 al2_6f dc $74be1c ;+0.9120517 al2_70 dc $756063 ;+0.9170040 al2_71 dc $76038c ;+0.9219832 al2_72 dc $76a798 ;+0.9269896 al2_73 dc $774c88 ;+0.9320230 al2_74 dc $77f25d ;+0.9370838 al2_75 dc $789918 ;+0.9421721 al2_76 dc $7940bc ;+0.9472880 al2_77 dc $79e948 ;+0.9524317 al2_78 dc $7a92bf ;+0.9576033 al2_79 dc $7b3d21 ;+0.9628030 al2_7a dc $7be870 ;+0.9680309 al2_7b dc $7c94ad ;+0.9732872 al2_7c dc $7d41d9 ;+0.9785720 al2_7d dc $7deff7 ;+0.9838856 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap rom and data rom contents motorola dsp56004 user? manual a-13 al2_7e dc $7e9f06 ;+0.9892280 al2_7f dc $7f4f09 ;+0.9945995 a.6 sine wave table (y data rom) org y:$100 ; s_00 dc $000000 ; +0.0000000000 s_01 dc $03242b ; +0.0245412998 s_02 dc $0647d9 ; +0.0490676016 s_03 dc $096a90 ; +0.0735644996 s_04 dc $0c8bd3 ; +0.0980170965 s_05 dc $0fab27 ; +0.1224106997 s_06 dc $12c810 ; +0.1467303932 s_07 dc $15e214 ; +0.1709619015 s_08 dc $18f8b8 ; +0.1950902939 s_09 dc $1c0b82 ; +0.2191012055 s_0a dc $1f19f9 ; +0.2429800928 s_0b dc $2223a5 ; +0.2667128146 s_0c dc $25280c ; +0.2902846038 s_0d dc $2826b9 ; +0.3136816919 s_0e dc $2b1f35 ; +0.3368898928 s_0f dc $2e110a ; +0.3598949909 s_10 dc $30fbc5 ; +0.3826833963 s_11 dc $33def3 ; +0.4052414000 s_12 dc $36ba20 ; +0.4275551140 s_13 dc $398cdd ; +0.4496113062 s_14 dc $3c56ba ; +0.4713967144 s_15 dc $3f174a ; +0.4928981960 s_16 dc $41ce1e ; +0.5141026974 s_17 dc $447acd ; +0.5349975824 s_18 dc $471ced ; +0.5555701852 s_19 dc $49b415 ; +0.5758082271 s_1a dc $4c3fe0 ; +0.5956993103 s_1b dc $4ebfe9 ; +0.6152315736 s_1c dc $5133cd ; +0.6343932748 s_1d dc $539b2b ; +0.6531729102 s_1e dc $55f5a5 ; +0.6715589762 s_1f dc $5842dd ; +0.6895405054 s_20 dc $5a827a ; +0.7071068287 s_21 dc $5cb421 ; +0.7242470980 s_22 dc $5ed77d ; +0.7409511805 s_23 dc $60ec38 ; +0.7572088242 s_24 dc $62f202 ; +0.7730104923 s_25 dc $64e889 ; +0.7883464098 s_26 dc $66cf81 ; +0.8032075167 s_27 dc $68a69f ; +0.8175848722 s_28 dc $6a6d99 ; +0.8314697146 s_29 dc $6c2429 ; +0.8448535204 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-14 dsp56004 user? manual motorola bootstrap rom and data rom contents s_2a dc $6dca0d ; +0.8577286005 s_2b dc $6f5f03 ; +0.8700870275 s_2c dc $70e2cc ; +0.8819212914 s_2d dc $72552d ; +0.8932244182 s_2e dc $73b5ec ; +0.9039893150 s_2f dc $7504d3 ; +0.9142097235 s_30 dc $7641af ; +0.9238795042 s_31 dc $776c4f ; +0.9329928160 s_32 dc $788484 ; +0.9415441155 s_33 dc $798a24 ; +0.9495282173 s_34 dc $7a7d05 ; +0.9569402933 s_35 dc $7b5d04 ; +0.9637761116 s_36 dc $7c29fc ; +0.9700313210 s_37 dc $7ce3cf ; +0.9757022262 s_38 dc $7d8a5f ; +0.9807853103 s_39 dc $7e1d94 ; +0.9852777123 s_3a dc $7e9d56 ; +0.9891765118 s_3b dc $7f0992 ; +0.9924796224 s_3c dc $7f6237 ; +0.9951847792 s_3d dc $7fa737 ; +0.9972904921 s_3e dc $7fd888 ; +0.9987955093 s_3f dc $7ff622 ; +0.9996988773 s_40 dc $7fffff ; +0.9999998808 s_41 dc $7ff622 ; +0.9996988773 s_42 dc $7fd888 ; +0.9987955093 s_43 dc $7fa737 ; +0.9972904921 s_44 dc $7f6237 ; +0.9951847792 s_45 dc $7f0992 ; +0.9924796224 s_46 dc $7e9d56 ; +0.9891765118 s_47 dc $7e1d94 ; +0.9852777123 s_48 dc $7d8a5f ; +0.9807853103 s_49 dc $7ce3cf ; +0.9757022262 s_4a dc $7c29fc ; +0.9700313210 s_4b dc $7b5d04 ; +0.9637761116 s_4c dc $7a7d05 ; +0.9569402933 s_4d dc $798a24 ; +0.9495282173 s_4e dc $788484 ; +0.9415441155 s_4f dc $776c4f ; +0.9329928160 s_50 dc $7641af ; +0.9238795042 s_51 dc $7504d3 ; +0.9142097235 s_52 dc $73b5ec ; +0.9039893150 s_53 dc $72552d ; +0.8932244182 s_54 dc $70e2cc ; +0.8819212914 s_55 dc $6f5f03 ; +0.8700870275 s_56 dc $6dca0d ; +0.8577286005 s_57 dc $6c2429 ; +0.8448535204 s_58 dc $6a6d99 ; +0.8314697146 s_59 dc $68a69f ; +0.8175848722 s_5a dc $66cf81 ; +0.8032075167 s_5b dc $64e889 ; +0.7883464098 s_5c dc $62f202 ; +0.7730104923 s_5d dc $60ec38 ; +0.7572088242 s_5e dc $5ed77d ; +0.7409511805 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap rom and data rom contents motorola dsp56004 user? manual a-15 s_5f dc $5cb421 ; +0.7242470980 s_60 dc $5a827a ; +0.7071068287 s_61 dc $5842dd ; +0.6895405054 s_62 dc $55f5a5 ; +0.6715589762 s_63 dc $539b2b ; +0.6531729102 s_64 dc $5133cd ; +0.6343932748 s_65 dc $4ebfe9 ; +0.6152315736 s_66 dc $4c3fe0 ; +0.5956993103 s_67 dc $49b415 ; +0.5758082271 s_68 dc $471ced ; +0.5555701852 s_69 dc $447acd ; +0.5349975824 s_6a dc $41ce1e ; +0.5141026974 s_6b dc $3f174a ; +0.4928981960 s_6c dc $3c56ba ; +0.4713967144 s_6d dc $398cdd ; +0.4496113062 s_6e dc $36ba20 ; +0.4275551140 s_6f dc $33def3 ; +0.4052414000 s_70 dc $30fbc5 ; +0.3826833963 s_71 dc $2e110a ; +0.3598949909 s_72 dc $2b1f35 ; +0.3368898928 s_5f dc $5cb421 ; +0.7242470980 s_60 dc $5a827a ; +0.7071068287 s_61 dc $5842dd ; +0.6895405054 s_62 dc $55f5a5 ; +0.6715589762 s_63 dc $539b2b ; +0.6531729102 s_64 dc $5133cd ; +0.6343932748 s_65 dc $4ebfe9 ; +0.6152315736 s_66 dc $4c3fe0 ; +0.5956993103 s_67 dc $49b415 ; +0.5758082271 s_68 dc $471ced ; +0.5555701852 s_69 dc $447acd ; +0.5349975824 s_6a dc $41ce1e ; +0.5141026974 s_6b dc $3f174a ; +0.4928981960 s_6c dc $3c56ba ; +0.4713967144 s_6d dc $398cdd ; +0.4496113062 s_6e dc $36ba20 ; +0.4275551140 s_6f dc $33def3 ; +0.4052414000 s_70 dc $30fbc5 ; +0.3826833963 s_71 dc $2e110a ; +0.3598949909 s_72 dc $2b1f35 ; +0.3368898928 s_73 dc $2826b9 ; +0.3136816919 s_74 dc $25280c ; +0.2902846038 s_75 dc $2223a5 ; +0.2667128146 s_76 dc $1f19f9 ; +0.2429800928 s_77 dc $1c0b82 ; +0.2191012055 s_78 dc $18f8b8 ; +0.1950902939 s_79 dc $15e214 ; +0.1709619015 s_7a dc $12c810 ; +0.1467303932 s_7b dc $0fab27 ; +0.1224106997 s_7c dc $0c8bd3 ; +0.0980170965 s_7d dc $096a90 ; +0.0735644996 s_7e dc $0647d9 ; +0.0490676016 s_7f dc $03242b ; +0.0245412998 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-16 dsp56004 user? manual motorola bootstrap rom and data rom contents s_80 dc $000000 ; +0.0000000000 s_81 dc $fcdbd5 ; -0.0245412998 s_82 dc $f9b827 ; -0.0490676016 s_83 dc $f69570 ; -0.0735644996 s_84 dc $f3742d ; -0.0980170965 s_85 dc $f054d9 ; -0.1224106997 s_86 dc $ed37f0 ; -0.1467303932 s_87 dc $ea1dec ; -0.1709619015 s_88 dc $e70748 ; -0.1950902939 s_89 dc $e3f47e ; -0.2191012055 s_8a dc $e0e607 ; -0.2429800928 s_8b dc $dddc5b ; -0.2667128146 s_8c dc $dad7f4 ; -0.2902846038 s_8d dc $d7d947 ; -0.3136816919 s_8e dc $d4e0cb ; -0.3368898928 s_8f dc $d1eef6 ; -0.3598949909 s_90 dc $cf043b ; -0.3826833963 s_91 dc $cc210d ; -0.4052414000 s_92 dc $c945e0 ; -0.4275551140 s_93 dc $c67323 ; -0.4496113062 s_94 dc $c3a946 ; -0.4713967144 s_95 dc $c0e8b6 ; -0.4928981960 s_96 dc $be31e2 ; -0.5141026974 s_97 dc $bb8533 ; -0.5349975824 s_98 dc $b8e313 ; -0.5555701852 s_99 dc $b64beb ; -0.5758082271 s_9a dc $b3c020 ; -0.5956993103 s_9b dc $b14017 ; -0.6152315736 s_9c dc $aecc33 ; -0.6343932748 s_9d dc $ac64d5 ; -0.6531729102 s_9e dc $aa0a5b ; -0.6715589762 s_9f dc $a7bd23 ; -0.6895405054 s_a0 dc $a57d86 ; -0.7071068287 s_a1 dc $a34bdf ; -0.7242470980 s_a2 dc $a12883 ; -0.7409511805 s_a3 dc $9f13c8 ; -0.7572088242 s_a4 dc $9d0dfe ; -0.7730104923 s_a5 dc $9b1777 ; -0.7883464098 s_a6 dc $99307f ; -0.8032075167 s_a7 dc $975961 ; -0.8175848722 s_a8 dc $959267 ; -0.8314697146 s_a9 dc $93dbd7 ; -0.8448535204 s_aa dc $9235f3 ; -0.8577286005 s_ab dc $90a0fd ; -0.8700870275 s_ac dc $8f1d34 ; -0.8819212914 s_ad dc $8daad3 ; -0.8932244182 s_ae dc $8c4a14 ; -0.9039893150 s_af dc $8afb2d ; -0.9142097235 s_b0 dc $89be51 ; -0.9238795042 s_b1 dc $8893b1 ; -0.9329928160 s_b2 dc $877b7c ; -0.9415441155 s_b3 dc $8675dc ; -0.9495282173 s_b4 dc $8582fb ; -0.9569402933 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap rom and data rom contents motorola dsp56004 user? manual a-17 s_b5 dc $84a2fc ; -0.9637761116 s_b6 dc $83d604 ; -0.9700313210 s_b7 dc $831c31 ; -0.9757022262 s_b8 dc $8275a1 ; -0.9807853103 s_b9 dc $81e26c ; -0.9852777123 s_ba dc $8162aa ; -0.9891765118 s_bb dc $80f66e ; -0.9924796224 s_bc dc $809dc9 ; -0.9951847792 s_bd dc $8058c9 ; -0.9972904921 s_be dc $802778 ; -0.9987955093 s_bf dc $8009de ; -0.9996988773 s_c0 dc $800000 ; -1.0000000000 s_c1 dc $8009de ; -0.9996988773 s_c2 dc $802778 ; -0.9987955093 s_c3 dc $8058c9 ; -0.9972904921 s_c4 dc $809dc9 ; -0.9951847792 s_c5 dc $80f66e ; -0.9924796224 s_c6 dc $8162aa ; -0.9891765118 s_c7 dc $81e26c ; -0.9852777123 s_c8 dc $8275a1 ; -0.9807853103 s_c9 dc $831c31 ; -0.9757022262 s_ca dc $83d604 ; -0.9700313210 s_cb dc $84a2fc ; -0.9637761116 s_cc dc $8582fb ; -0.9569402933 s_cd dc $8675dc ; -0.9495282173 s_ce dc $877b7c ; -0.9415441155 s_cf dc $8893b1 ; -0.9329928160 s_d0 dc $89be51 ; -0.9238795042 s_d1 dc $8afb2d ; -0.9142097235 s_d2 dc $8c4a14 ; -0.9039893150 s_d3 dc $8daad3 ; -0.8932244182 s_d4 dc $8f1d34 ; -0.8819212914 s_d5 dc $90a0fd ; -0.8700870275 s_d6 dc $9235f3 ; -0.8577286005 s_d7 dc $93dbd7 ; -0.8448535204 s_d8 dc $959267 ; -0.8314697146 s_d9 dc $975961 ; -0.8175848722 s_da dc $99307f ; -0.8032075167 s_db dc $9b1777 ; -0.7883464098 s_dc dc $9d0dfe ; -0.7730104923 s_dd dc $9f13c8 ; -0.7572088242 s_de dc $a12883 ; -0.7409511805 s_df dc $a34bdf ; -0.7242470980 s_e0 dc $a57d86 ; -0.7071068287 s_e1 dc $a7bd23 ; -0.6895405054 s_e2 dc $aa0a5b ; -0.6715589762 s_e3 dc $ac64d5 ; -0.6531729102 s_e4 dc $aecc33 ; -0.6343932748 s_e5 dc $b14017 ; -0.6152315736 s_e6 dc $b3c020 ; -0.5956993103 s_e7 dc $b64beb ; -0.5758082271 s_e8 dc $b8e313 ; -0.5555701852 s_e9 dc $bb8533 ; -0.5349975824 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-18 dsp56004 user? manual motorola bootstrap rom and data rom contents s_ea dc $be31e2 ; -0.5141026974 s_eb dc $c0e8b6 ; -0.4928981960 s_ec dc $c3a946 ; -0.4713967144 s_ed dc $c67323 ; -0.4496113062 s_ee dc $c945e0 ; -0.4275551140 s_ef dc $cc210d ; -0.4052414000 s_f0 dc $cf043b ; -0.3826833963 s_f1 dc $d1eef6 ; -0.3598949909 s_f2 dc $d4e0cb ; -0.3368898928 s_f3 dc $d7d947 ; -0.3136816919 s_f4 dc $dad7f4 ; -0.2902846038 s_f5 dc $dddc5b ; -0.2667128146 s_f6 dc $e0e607 ; -0.2429800928 s_f7 dc $e3f47e ; -0.2191012055 s_f8 dc $e70748 ; -0.1950902939 s_f9 dc $ea1dec ; -0.1709619015 s_fa dc $ed37f0 ; -0.1467303932 s_fb dc $f054d9 ; -0.1224106997 s_fc dc $f3742d ; -0.0980170965 s_fd dc $f69570 ; -0.0735644996 s_fe dc $f9b827 ; -0.0490676016 s_ff dc $fcdbd5 ; -0.0245412998 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual b-1 appendix a programming reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-2 dsp56004 user? manual motorola programming reference a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.2 peripheral addresses. . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.3 interrupt addresses . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.4 interrupt priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.5 instruction set summary. . . . . . . . . . . . . . . . . . . . . . a-3 a.6 programming sheets . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-3 a.1 introduction this section has been compiled as a reference for programmers. it contains a memory map showing the addresses of all the dsp? memory-mapped peripherals, an interrupt priority table, an instruction set summary, and programming sheets for all the programmable registers on the dsp. the programming sheets are grouped by the central processor and each peripheral, and provide room to write in the value of each bit and the hexadecimal value for each register. the programmer can photocopy these sheets and reuse them for each application development project. a.2 peripheral addresses figure a-1 is a memory map of the on-chip peripherals showing their addresses in memory. a.3 interrupt addresses table a-1 on page b-5 lists the interrupt starting addresses and sources. a.4 interrupt priorities table a-2 on page b-6 lists the priorities of specific interrupts within interrupt priority levels. a.5 instruction set summary table a-3 on page b-7 summarizes the instruction set. for more detailed information about the instructions, consult the dsp56000 family manual . a.6 programming sheets figure a-2 on page b-14 through figure a-17 on page b-29 are programming sheets for the complete set of programmable registers on the dsp. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-4 dsp56004 user? manual motorola programming reference figure a-1 on-chip peripheral memory map 23 16 15 8 7 0 x:$ffff interrupt priority register (ipr) x:$fffe reserved x:$fffd pll control register (pctl) x:$fffc reserved x:$fffb reserved x:$fffa reserved x:$fff9 reserved x:$fff8 reserved x:$fff7 gpio control/data register (gpior) x:$fff6 emi write offset register (ewor) x:$fff5 reserved x:$fff4 reserved x:$fff3 shi receive fifo/transmit register (hrx/htx) x:$fff2 shi i 2 c slave address register (hsar) x:$fff1 shi host control/status register (hcsr) x:$fff0 shi host clock control register (hckr) x:$ffef emi refresh control register (ercr) x:$ffee emi data register 1 (edrr1/edwr1) x:$ffed emi offset register 1 (eor1) x:$ffec emi base address register 1 (ebar1) x:$ffeb emi control/status register (ecsr) x:$ffea emi data register 0 (edrr0/edwr0) x:$ffe9 emi offset register 0 (eor0) x:$ffe8 emi base address register 0 (ebar0) x:$ffe7 sai tx2 data register (tx2) x:$ffe6 sai tx1 data register (tx1) x:$ffe5 sai tx0 data register (tx0) x:$ffe4 sai tx control/status register (tcs) x:$ffe3 sai rx1 data register (rx1) x:$ffe2 sai rx0 data register (rx0) x:$ffe1 sai rx control/status register (rcs) x:$ffe0 sai baud rate control register (brc) x:$ffdf reserved x:$ffde reserved x:$ffdd reserved x:$ffdc reserved x:$ffdb reserved x:$ffda reserved x:$ffd9 reserved x:$ffd8 reserved x:$ffd7 reserved x:$ffd6 reserved x:$ffd5 reserved x:$ffd4 reserved x:$ffd3 reserved x:$ffc0 reserved = unused and reserved. read as a random number. to ensure future compatibility, do not write to these registers. = unused and reserved. consult the appropriate chapter for information on how to ensure future compatibility. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-5 table a-1 interrupt starting addresses and sources interrupt starting address ipl interrupt source p:$0000 3 hardware reset p:$0002 3 stack error p:$0004 3 trace p:$0006 3 swi p:$0008 0? irqa p:$000a 0? irqb p:$000c reserved p:$000e reserved p:$0010 0? sai left channel transmitter if txil = 0 p:$0012 0? sai right channel transmitter if txil = 0 p:$0014 0? sai transmitter exception if txil = 0 p:$0016 0? sai left channel receiver if rxil = 0 p:$0018 0? sai right channel receiver if rxil = 0 p:$001a 0? sai receiver exception if rxil = 0 p:$001c reserved p:$001e 3 nmi p:$0020 0? shi transmit data p:$0022 0? shi transmit underrun error p:$0024 0? shi receive fifo not empty p:$0026 reserved p:$0028 0? shi receive fifo full p:$002a 0? shi receive overrun error p:$002c 0? shi bus error p:$002e reserved p:$0030 0? emi write data p:$0032 0? emi read data p:$0034 0? emi ebar0 memory wrap p:$0036 0? emi ebar1 memory wrap p:$0038 reserved p:$003a reserved p:$003c reserved p:$003e 3 illegal instruction p: $0040 0? sai left channel transmitter if txil = 1 p: $0042 0? sai right channel transmitter if txil = 1 p: $0044 0? sai transmitter exception if txil = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-6 dsp56004 user? manual motorola programming reference p: $0046 0? sai left channel receiver if rxil = 1 p: $0048 0? sai right channel receiver if rxil = 1 p: $004a 0? sai receiver exception if rxil = 1 p: $004c reserved :: p: $007e reserved table a-2 interrupt priorities within an ipl priority interrupt level 3 (nonmaskable) highest hardware reset illegal instruction nmi stack error trace lowest swi levels 0, 1, 2 (maskable) highest irqa (external interrupt) irqb (external interrupt) sai receiver exception sai transmitter exception sai left channel receiver sai left channel transmitter sai right channel receiver sai right channel transmitter shi bus error shi receive overrun error shi transmit underrun error shi receive fifo full shi transmit data shi receive fifo not empty emi ebar0 memory wrap emi ebar1 memory wrap emi read data lowest emi write data table a-1 interrupt starting addresses and sources (continued) interrupt starting address ipl interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-7 table a-3 instruction set summary (sheet 1 of 7) mnemonic syntax parallel moves instruction program words osc. clock cycles status request bits: sleunzvc abs d (parallel move) 1 + mv 2 + mv * * * * * * * adc s,d (parallel move) 1 + mv 2 + mv * * * * * * * * add s,d (parallel move) 1 + mv 2 + mv * * * * * * * * addl s,d (parallel move) 1 + mv 2 + mv * * * * * * ? * addr s,d (parallel move) 1 + mv 2 + mv * * * * * * * * and s,d (parallel move) 1 + mv 2 + mv * * ? ? 0 and(i) #xx,d 1 2 ? ? ? ? ? ? ? ? asl d (parallel move) 1 + mv 2 + mv * * * * * * ? ? asr d (parallel move) 1 + mv 2 + mv * * * * * * 0 ? bchg #n,x: b-8 dsp56004 user? manual motorola programming reference btst #n,x: programming reference motorola dsp56004 user? manual b-9 jmp xxxx 1 + ea 4 + jx ea jscc xxxx 1 + ea 4 + jx ea jsclr #n,x: b-10 dsp56004 user? manual motorola programming reference ( )s,#n,d ( no parallel move) 1 2 macr ( )s2,s1,d (parallel move) 1 + mv 2 + mv * * * * * * * ( )s1,s2,d (parallel move) ( )s,#n,d ( no parallel move) 1 2 move s,d 1 + mv 2 + mv * * no parallel data move (.....) mv mv immediate short (.....)#xx,d mv mv data move register to register (.....)s,d mv mv * * data move address register update (.....)ea mv mv x memory data move (.....)x: programming reference motorola dsp56004 user? manual b-11 long memory data move (.....)l: b-12 dsp56004 user? manual motorola programming reference move(p) (continued) y: programming reference motorola dsp56004 user? manual b-13 rol d (parallel move) 1 + mv 2 + mv * * ? ? 0 ? ror d (parallel move) 1 + mv 2 + mv * * ? ? 0 ? rti 1 4 + rx ? ? ? ? ? ? ? ? rts 1 4 + rx sbc s,d (parallel move) 1 + mv 2 + mv * * * * * * * * stop 1 n/a sub s,d (parallel move) 1 + mv 2 + mv * * * * * * * * subl s,d (parallel move) 1 + mv 2 + mv * * * * * * ? * subr s,d (parallel move) 1 + mv 2 + mv * * * * * * * * swi 1 8 tcc s1,d1 1 2 s1,d1 s2,d2 tfr s,d (parallel move) 1 + mv 2 + mv * * tst s (parallel move) 1 + mv 2 + mv * * * * * * 0 wait 1 n/a table a-3 instruction set summary (sheet 7 of 7) mnemonic syntax parallel moves instruction program words osc. clock cycles status request bits: sleunzvc ?indicates that the bit is unaffected by the operation * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. see the instruction descriptions in appendix a of the dsp56000 family manual (dsp56kfamum/ad) 0 indicates that the bit is cleared f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-14 dsp56004 user? manual motorola programming reference figure a-2 status register (sr) central processor application: date: programmer: sheet 1 of 4 carry overflow zero negative unnormalized extension limit fft scaling interrupt mask scaling mode reserved trace mode double precision multiply mode loop flag 1514131211109876543210 lf t s1 s0 i1 i0 l e u n z v c status register (sr) read/write reset = $0300 dm s mode register (mr) condition code register (ccr) * = reserved, write as 0 * 0 note: the operation and function of the status register is detailed in the dsp56000 family manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-15 figure a-3 interrupt priority register (ipr) application: date: programmer: sheet 2 of 4 central processor * = reserved, write as 0 sal1 sal0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 1514131211109876543210 eml0 sal1 sal0 ibl2 ibl1 ibl0 ial2 ial1 ial0 interrupt priority x:$ffff read/write shl1 shl0 reset = $000000 register (ipr) 23 22 21 20 19 18 16 17 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 eml1 00 sai ipl shl1 shl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 shi ipl eml1 eml0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 emi ipl ila2 trigger 0 level 1 neg. edge irqb mode ibl1 ibl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 ila2 trigger 0 level 1 neg. edge irqa mode ial1 ial0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-16 dsp56004 user? manual motorola programming reference figure a-4 operating mode register (omr) application: date: programmer: sheet 3 of 4 central processor operating mode read/write reset = $000000 register (omr) 1514131211109876543210 sd mc mb ma ** 0 0 ** 0 0 ** 0 0 ** 0 0 00 00 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 * 0 * 0 stop delay 0 = 128k t stabilization 1 = 16 t stabilization * = bits 5 and 7 through 23 are reserved, write as 0 mode m m m c b a operating mode 0 0 0 0 normal operation, bootstrap disabled 1 0 0 1 bootstrap from emi 2 0 1 0 wake up in prom address $2000 3 0 1 1 reserved 4 1 0 0 reserved 5 1 0 1 bootstrap from shi (spi) 6 1 1 0 reserved 7 1 1 1 bootstrap from shi (i 2 c) * 0 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-17 figure a-5 pll control register (pctl) application: date: programmer: sheet 4 of 4 central processor 1514131211109876543210 df3 df2 mf11 mf10 mf7 mf6 mf5 mf4 mf3 mf2 mf1 mf0 pll contro l x:$fffd read/write df1 df0 reset = $0001f3(pinit = gnd) register (pctl) 19 18 17 16 23 22 21 20 * 0 mf8 mf9 pstp pen csrc multiplication factor bits mf0?f11 mf11?f0 multiplication factor mf $000 1 $001 2 $002 3 $ffe 4095 $fff 4096 stop processing state bit (pstp) 0 = pll disabled during stop processing state 1 = pll enabled during stop processing state pll enable bit (pen) 0 = disable pll 1 = enable pll chip clock source bit (csrc) 0 = output from low power divider 1 = output from vco * = reserved, write as 0 * 0 * 0 * 0 * 0 division factor bits df0?f11 df11?f0 division factor mf $0 2 0 $1 2 1 $2 2 2 $e 2 14 $f 2 15 reset = $0401f3 (pinit=vcc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-18 dsp56004 user? manual motorola programming reference figure a-6 emi control/status register (ecsr) emi addressing modes eam (3:0) type addressing address lines chip select ras/cas 0000 sram absolute ma(14:0) none refresh only 0001 sram relative ma(17:0) mcs0 n.a. 0010 sram relative ma(16:0) mcs(1:0) n.a. 0011 sram relative ma(14:0) mcs(3:0) n.a. 0100 dram relative ma(7:0) n.a. yes 0101 dram relative ma(8:0) n.a. yes 0110 dram relative ma(9:0) n.a. yes 0111 dram relative ma(10:0) n.a. yes 1100 dram absolute ma(7:0) n.a. yes 1101 dram absolute ma(8:0) n.a. yes 1110 dram absolute ma(9:0) n.a. yes 1111 dram absolute ma(10:0) n.a. yes 1514131211109876543210 ebsy ebdf eis1 einr eam3 eam1 eam0 ewl1 ewl0 ebw emi control/status edrf edwe reset = $7c0000 register (ecsr) 19 18 17 16 23 22 21 20 einw eis0 erts edtm estm0 estm1 estm2 estm3 x:$ffeb write/read eme ecsr increment ebar after write (einw) 0 = ebar unmodified after write 1 = ebar incremented after write ecsr data write register empty (edwe) 0 = edwr full1 = edwr empty read only status bit ecsr data read register full (edrf) 0 = eddr empty1 = edrr full read only status bit ecsr data register buffer and data read register full (ebdf) read only status bit 0 = input registers not full 1 = data register buffer and data read register full ecsr emi busy (ebsy) read only status bit 0 = no transfers, no requests pending 1 = transfers and/or requests pending ecsr read trigger select (erts) 0 = triggered by write to eor 1 = triggered by read from edrr ecsr emi enable (eme) 0 = individual reset 1 = transfers enabled ecsr data bus width (ebw) 0 = 4 bits 1 = 8 bits ecsr increment ebar after read (einr) 0 = ebar unmodified after read 1 = ebar incremented after read ewl2 emwie eam2 ecsr memory wrap interrupt enable (emwie) 0 = interrupt disabled 1 = interrupt enabled e.m.i. emi dram timing (relative addressing) word length bus width edtm=1 edtm=0 8 8 12 16 12 or 16 20 24 20 or 24 refresh 4 8 4 4 8 4 4 8 16 12 20 24 16 28 32 20 12 11 8 14 17 11 20 23 14 8 ecsr sram timing (estm0?stm3) word length bus width clock cycles 8 8 12 16 12 or 16 20 24 20 or 24 4 8 4 4 8 4 4 8 2 (4 + estm) 1 (4 + estm) 3 (4 + estm) 4 (4 + estm) 2 (4 + estm) 5 (4 + estm) 6 (4 + estm) 3 (4 + estm) ewl(2:0) word length 000 001 010 011 100 101 110 111 8 bit data word 16 bit data word 24 bit data word 16 bit data/24 bit addr. reserved 12 bit data word 20 bit data word reserved eis1 eis0 read/write interrupt select 0 0 read/write interrupts disabled 0 1 write int. vector on edwe = 1 1 0 read int. vector on edrf = 1 1 1 read int. vector on ebdf = 1 emi dram timing (absolute addressing) n 12for edtm = 1 n 8 for edtm = 0 where n is the no. of accesses in a word transfer application: date: programmer: sheet 1 of 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-19 figure a-7 emi base address and offset registers application: date: programmer: sheet 2 of 4 e.m.i. 1514131211109876543210 emi base address x:$ffe8 read/write reset = $xxxxxx register 0 (ebar0) 19 18 17 16 23 22 21 20 base address register 0 contents 1514131211109876543210 emi base address x:$ffec read/write reset = $xxxxxx register 1 (ebar1) 19 18 17 16 23 22 21 20 base address register 1 contents 1514131211109876543210 emi read offset x:$ffe9 (eor0) reset = $000000 register?ead/write 19 18 17 16 23 22 21 20 read offset register contents 1514131211109876543210 emi write offset x:$ffe6 read/write reset = $000000 register (ewor) 19 18 17 16 23 22 21 20 write offset register contents x:$ffed (eor1) emi write offset register (ewor) emi read offset register ?read/write emi base address register 1 (ebar1) emi base address register 0 (ebar0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-20 dsp56004 user? manual motorola programming reference figure a-8 emi data registers emi data read x:$ffea (edrr0) reset = $xxxxxx register?ead only x:$ffee (edrr1) application: date: programmer: sheet 3 of 4 e.m.i. 1514131211109876543210 19 18 17 16 23 22 21 20 data read register contents 1514131211109876543210 19 18 17 16 23 22 21 20 data write register contents emi data write register ?write only emi data read register ?read only emi data write x:$ffea (edwr0) reset = $xxxxxx register?rite only x:$ffee (edwr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-21 figure a-9 emi refresh control register (ercr) application: date: programmer: sheet 4 of 4 e.m.i. 1514131211109876543210 ecd7 ecd5 ecd4 ecd3 ecd2 ecd1 ecd0 emi refresh control x:$ffef read/write reset = $000000 register (ercr) 19 18 17 16 23 22 21 20 eps0 eps1 eosr ered * = reserved, write as 0 * 0 * 0 eref ecd6 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 refresh rate preset value ercr refresh clock prescaler (eps0?ps1) eps1 eps0 interrupt select 0 0 divide by 64 0 1 divide by 8 1 0 prescaler bypassed 1 1 reserved ercr one-shot refresh (eosr) 0 = no refresh 1 = refresh trigger ercr refresh enable (eref) 0 = refresh cycle insertion disabled 1 =cas before ras refresh cycle inserted 00 ercr refresh enable when debugging (ered) 0 = don? override eref 1 = refresh during debug?verride eref f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-22 dsp56004 user? manual motorola programming reference figure a-10 shi slave address and clock control registers application: date: programmer: sheet 1 of 3 s.h.i. * = reserved, write as 0 1514131211109876543210 hdm4 hdm2 hdm1 hdm0 hrs cpol cpha shi clock control x:$fff0 reset = $000001 register (hckr) 19 18 17 16 23 22 21 20 * 0 * 0 hdm3 * 0 * 0 * 0 * 0 * 0 * 0 * 0 1514131211109876543210 shi slave address x:$fff2 reset = $bx0000 register (hsar) 19 18 17 16 23 22 21 20 ha1 ha3 ha5 * 0 * 0 ha6 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 ha4 0 0 0 0 * 0 * 0 * 0 * 0 00 hdm5 hckr divider modulus select hsar i 2 c slave address slave address = bits ha6?a3, ha1 and external pins ha2, ha0 slave address after reset = 1011_ha2_0_ha0 hfm1 hfm0 shi noise reduction filter mode 0 0 bypassed (filter disabled) 0 1 reserved 1 0 narrow spike tolerance 1 1 wide spike tolerance hfm0 hfm1 shi clock control register (hckr) shi slave address register (hsar) cpol cpha result 0 0 sck active low, strobe on rising edge 0 1 sck active low, strobe on falling edge 1 0 sck active high, strobe on falling edge 1 1 sck active high, strobe on rising edge hrs result 0 prescaler operational 1 prescaler bypassed f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-23 figure a-11 shi host data registers application: date: programmer: sheet 2 of 3 s.h.i. 1514131211109876543210 shi host transmit x:$fff3 write only reset = $xxxxxx data register (htx) 19 18 17 16 23 22 21 20 host transmit data register contents 1514131211109876543210 shi host receive x:$fff3 read only reset = $xxxxxx data register (hrx) 19 18 17 16 23 22 21 20 host receive data register contents shi host receive data register (hrx) shi host transmit data register (htx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-24 dsp56004 user? manual motorola programming reference figure a-12 shi control/status register (hcsr) s.h.i. * = reserved, write as 0 1514131211109 8 7 6543210 hrqe0 hfif0 hm1 hm0 hi 2 c hen shi control/status x:$fff1 reset = $008200 register (hcsr) 19 18 17 16 23 22 21 20 hrff hroe hbusy * 0 hmst * 0 htie hbie hidle hrqe1 htde htue hrie1 hrie0 hrne hber hen description 0 shi disabled 1 shi enabled hi 2 c result 0 spi mode 1i 2 c mode hm1 hm0 description 0 0 8 bit data 0 1 16 bit data 1 0 24 bit data 1 1 reserved hfifo description 0 1 level fifo 1 10 level fifo hmst result 0 slave mode 1 master mode hrqe1 hrqe0 hreq pin operation 0 0 high impedance 0 1 asserted if iosr ready to receive new word 1 0 asserted if iosr ready to transmit new word 11i 2 c: asserted if iosr ready to transmit or receive spi: asserted if iosr ready to transmit and receive hidle description 0 bus busy 1 stop event hbie description 0 bus error interrupt disabled 1 bus error interrupt enabled htie description 0 transmit interrupt disabled 1 transmit interrupt activated host transmit underrun error read only status bit host transfer data empty read only status bit host receive fifo not empty read only status bit host receive fifo full read only status bit host receive overrun error read only status bit * 0 hber i 2 c spi mode 0 no error no error 1 no acknowledge ss asserted hbusy i 2 c spi mode 0 stop event not busy 1 shi detects start ss detected (slave) -or- htx/iosr not empty (master) hrie1 hrie0 interrupt condition 00 1 0 1 disabled receive fifo not empty receive overrun error reserved receive fifo full receive overrun error n.a. hrne=1 & hroe=0 hroe=1 n.a. hrff=1 & hroe=0 hroe=1 0 1 1 application: date: programmer: sheet 3 of 3 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-25 figure a-13 sai receiver control/status register (rcs) application: date: programmer: sheet 1 of 4 s.a.i. 1514131211109876543210 receiver control/status x:$ffe1 reset = $0000 register (rcs) r0en r1en rmst rwl0 * rwl1 rlrs rckp rdir * 0 rdwt rxie rrel rldf rrdf r0en description 0 receiver 0 disabled 1 receiver 0 enabled r1en description 0 receiver 1 disabled 1 receiver 1 enabled rmst description 0 sai slave 1 sai master rwl1 rwl0 bits/word 0016 0124 1032 1 1 reserved rdir description 0 data shifted in msb first 1 data shifted in lsb first rlrs description 0 wsr low identifies left data word; wsr high identifies right data word 1 wsr high identifies left data word; wsr low identifies right data word rckp description 0 polarity is negative 1 polarity is positive rrel description 0 wsr occurs with 1st bit 1 wsr occurs 1 cycle earlier rdwt description 0 first 24 bits transferred 1 last 24 bits transferred rxil description 0 rx interrupt vector location at $1x 1 rx interrupt vector location at $4x rldf description?ead only status bit 0 left data register empty 1 left data register full rrdf description?ead only 0 right data register empty 1 right data register full 0 rxie description 0 receiver interrupts disabled 1 receiver interrupts enabled rxil * = reserved, write as 0 23 16 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-26 dsp56004 user? manual motorola programming reference figure a-14 sai transmitter control/status register (tcs) application: date: programmer: sheet 2 of 4 s.a.i. 1514131211109876543210 transmitter control/ x:$ffe4 reset = $0000 status register (tcs) t0en t1en tmst twl0 * 0 twl1 tlrs tckp tdir tdwe txie trel tlde trde t2en t0en description 0 transmitter 0 disabled 1 transmitter 0 enabled t2en description 0 transmitter 2 disabled 1 transmitter 2 enabled t1en description 0 transmitter 1 disabled 1 transmitter 1 enabled twl1 twl0 number of bits/word 0016 0124 1032 1 1 reserved tdir description 0 data shifted out msb first 1 data shifted out lsb first tlrs description 0 wst low identifies left data word; wst high identifies right data word 1 wst high identifies left data word; wst low identifies right data word tckp description 0 polarity is negative 1 polarity is positive trel description 0 wsr occurs with 1st bit 1 wsr occurs 1 cycle earlier tdwe description 0 last bit transmitted 8 times 1 first bit transmitted 8 times txie description 0 transmitter interrupts disabled 1 transmitter interrupts enabled tlde description?ead only 0 left data register full 1 left data register empty trde description?ead only 0 right data register full 1 right data register empty tmst description 0 sai slave 1 sai master txil description 0 tx interrupt vector location at $1x 1 tx interrupt vector location at $4x txil * = reserved, write as 0 23 16 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-27 figure a-15 sai baud rate control and receive data registers application: date: programmer: sheet 3 of 4 s.a.i. 1514131211109876543210 sai receive data x:$ffe2 read only reset = $xxxxxx register 0 (rx0) 19 18 17 16 23 22 21 20 receive data register 0 contents 1514131211109876543210 sai receive data x:$ffe3 read only reset = $xxxxxx register 1 (rx1) 19 18 17 16 23 22 21 20 receive data register 1 contents sai receive data register 1 (rx1) sai receive data register 0 (rx0) 15 14 13 12 11109876543210 baud rate control x:$ffe0 reset = $0000 register (brc) pm0 pm1 pm3 * 0 pm4 * 0 * 0 * 0 * 0 * 0 * 0 pm2 0 pm5 pm7 psr pm6 psr description 0 divide by 8 prescaler operational 1 divide by 8 prescaler bypassed prescale modulus select for sai baud rate generator * = bits 9 through 23 are reserved. write as 0 baud rate control register (brc) 23 16 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-28 dsp56004 user? manual motorola programming reference figure a-16 sai transmit data registers application: date: programmer: sheet 4 of 4 s.a.i. 1514131211109876543210 sai transmit data x:$ffe7 write only reset = $xxxxxx register 2 (tx2) 19 18 17 16 23 22 21 20 transmit data register 2 contents 1514131211109876543210 sai transmit data x:$ffe5 write only reset = $xxxxxx register 0 (tx0) 19 18 17 16 23 22 21 20 transmit data register 0 contents 1514131211109876543210 sai transmit data x:$ffe6 write only reset = $xxxxxx register 1 (tx1) 19 18 17 16 23 22 21 20 transmit data register 1 contents sai transmit data register 2 (tx2) sai transmit data register 0 (tx0) sai transmit data register 1 (tx1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-29 figure a-17 gpio control/data register (gpior) application: date: programmer: sheet 1 of 1 gpio * = reserved, write as 0 1514131211109876543210 gd3 gd2 gd1 gd0 gpio control/data x:$fff7 reset = $000000 register (gpior) 19 18 17 16 23 22 21 20 gc3 * 0 gdd3 gdd2 gdd1 gdd0 gc1 gcx gddx gpio pin definition 0 0 disconnected 0 1 standard output 1 0 input 1 1 open-drain output * 0 * 0 * 0 0 * 0 * 0 * 0 * 0 0 gc0 gc2 * 0 * 0 * 0 * 0 0 gpio data bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-30 dsp56004 user? manual motorola programming reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual a-1 appendix a application examples f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-2 dsp56004 user? manual motorola application examples a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.2 typical system topology. . . . . . . . . . . . . . . . . . . . . . a-3 a.3 program overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.4 single delay line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.5 early reflection filter . . . . . . . . . . . . . . . . . . . . . . . a-5 a.6 two channel comb filter . . . . . . . . . . . . . . . . . . . . . . a-6 a.7 3-tap fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . application examples motorola dsp56004 user? manual a-3 a.1 introduction several examples illustrating the use of the dsp in common audio applications are presented in this section. the examples assume that the dsp is in the sram mode and configured for 0 wait states, 24-bit words, and an 8-bit bus (12 clock cycles-per-word transfer). a.2 typical system topology figure a-1 shows the topology of a typical dsp audio application. figure a-1 topology of dsp typical audio application i 2 s/sony i 2 s/sony consumer tr0 tr1 stereo a/d i 2 s/sony rec0 sram/ dram extal md7:0 ma17:0 host shi stereo a/d rec1 tr2 external sinusoidal clock source i 2 s/sony i 2 s/sony gpio audio dsp processor stereo d/a stereo d/a stereo d/a left front right front left rear right rear left effects right effects aa0259k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-4 dsp56004 user? manual motorola application examples a.3 program overlay the following routine illustrates a program overlay by replacing n instruction words in the internal program memory. the emi operates in the linear sram mode (eam (3:0) = 0) with 0 wait states. it is also assumed that the external memory device (eprom/sram) receives its chip select from gpio3. overlay movep #ol_sram,x:ecsr ; ram definition movep $000f07x,x:gpior ; assert gpio3 - enable cs movep #>ext_prog_buf,x:ebar0 ; start address of external buffer movep #0,x:eor0 ; drive 1st read trigger move #>int_prog_buf,r0 ; start address of internal buffer movep #0,x: eor0 ; drive 2nd read trigger bset #erts,x:ecsr ; set read triggers by reading eddr do #(n-2),end_ol ; loop to drive more (n-2) triggers rep #1 nop movep x:edrr0,p:(r0)+ ; move previous read data to pmem and ; trigger next read cycle end_ol bclr #erts,x:ecsr ; turn off read triggers by edrr read movep x:edrr0,p:(r0)+ ; move instruction #n-1 to pmem movep x: edrr0,p:(r0)+ ; move instruction #n to pmem bset #gpior,x:gpior ; negate gpio3 - disable cs a.4 single delay line the following routine is an example of a single delay line, as illustrated in figure a-2 . this type of routine is typically used in surround sound or reverb applications. delay_line movep #ram,x:ecsr ; use einr = 1. movep y:write_off,x:ewor ; optional change of write offset movep y:delay base,x:ebar0 ; load base address movep #(t_dly-1),x:eor0 ; read trigger for delayed sample movep x:sample,x:edwr0 ; write trigger for current sample movep x:ebar0,y:delay_base ; store updated base address nop ; nop or other movep x:edrr0,y0 ; read the delayed data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . application examples motorola dsp56004 user? manual a-5 a.5 early reflection filter the following routine is an example of an n-taps early reflection filter to perform the following computation: y (n) = sum [{i = 1...n} g(i) x(n-t (i))] movep #ram,x:ecsr ; ecsr with einw = 1 move #gain_base,r4 ; gain table base move #off_base,r0 ; offset table base movep y:fir_base,x:ebar0 ; fir base address movep x:(r0)+,x:eor0 ; drive 1st read cycle clr a x:(r0)+,x0 y:(r4)+,y0 ; fetch 1st gain and 2nd delay do #(n-1),end_e movep x0,x:eor0 ; initiate next read ; trigger nop ; nop or other nop ; nop or other movep x:edrr0,x1 ; read current data mac x1,y0,a x:(r0)+,x0 y:(r4)+,y0 ; sum, fetch next gain and offset nop ; nop or other end_e movep x:sample,x:edwr0 ; write current sample to delay line. ; ewor = 0 nop ; nop or other movep x:edrr0,x1 ; read last data macr x1,y0,a ; compute the output movep x:ebar0,y:fir_base ; store fir base move a,x:fir_output ; store result in internal memory figure a-2 single delay line delay t x(n) x(n - t) current sample delayed sample aa0447 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-6 dsp56004 user? manual motorola application examples a.6 two channel comb filter the following program implements a two channel (left and right) comb filter structure in which gain and delays are not equal. this type of program is typically used in surround sound and reverb applications. the filter structure is illustrated in figure a-3 . this example makes extensive use of the dual channel capability and pipeline mechanism of the emi. the code is optimized for sram (0 wait-state) 24-bit words and 8-bit bus (6 instruction cycles per access). in the event that another emi mode is being selected, nop instructions might be added in the noted points (#1, #2, and #3). the optimized code for fast dram mode, 24-bit words and 8-bit bus (7 i cyc per access and data available for read at last i cyc of the access) is achieved by adding 4 nop instructions at point #3. this code assumes ewor is already loaded with offset zero. ; dual_comb move # a-8 dsp56004 user? manual motorola application examples a.7 3-tap fir filter the following program implements a 3-tap fir filter. this type of program is typically used in generating early reflection information for surround sound and reverb applications. the filter structure is illustrated in figure a-4 . this code segment assumes accesses of 16-bit words on an 8-bit bus, ?ast?dram timing (26 instruction cycles), and 0-wait state sram timing (20 instruction cycles). number of memory storage locations = t3(seconds) fs (hz). for a 50 ms delay and 44.1 khz sampling rate: 0.05 44100 = 2205 locations. fir filter assembler code (emi mode: increment ebar on write operation): movep x:fir_base,x:ebar0 ; set fir base address movep #t1_off,x:eor0 ; offset t1 and trigger mem. read ; wait 3 (dram) or 1 (sram) inst. ; cycles or do other tasks movep #t2_off,x:eor0 ; offset t2 and trigger mem. read clr a x:g1,x0 ; get g1,clear accumulator movep x:edrr0,y0 ; get x(n-t1) movep #t3_off,x:eor0 ; offset t3 and trigger r mem. read mac x0,y0,a x:g2,x0 ; y(n) = g1 x(n-t1),get g2 ; wait 2 (dram) or 0(sram) ; inst. cycles or do other tasks movep x:edrr0,y0 ; get x(n-t2) mac x0,y0,a x:g3,x0 y(n) = y(n)+g2 x(n-t2) ; get g3, wait 4 (dram)or 2 (sram) inst. cycles ; or do other tasks movep x:edrr0,y0 ; get x(n-t3) movep x:sample,x:edwr0 ; store x(n) in mem. mac x0,y0,a ; calculate y(n) = y(n) + g3 x(n-t3) figure a-4 3 tap fir filter delay t1 gain g1 y(n) = g1 x (n - t1) + g2 x (n - t2) + g3 x (n - t3) x(n) delay t2 delay t3 gain g2 gain g3 x(n-t1) x(n-t2) x(n-t3) + aa0449 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004 user? manual b-1 appendix b programming reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-2 dsp56004 user? manual motorola programming reference b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 peripheral addresses. . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.3 interrupt addresses . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.4 interrupt priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.5 instruction set summary. . . . . . . . . . . . . . . . . . . . . . b-3 b.6 programming sheets . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-3 b.1 introduction this section has been compiled as a reference for programmers. it contains a memory map showing the addresses of all the dsp? memory-mapped peripherals, an interrupt priority table, an instruction set summary, and programming sheets for all the programmable registers on the dsp. the programming sheets are grouped by the central processor and each peripheral, and provide room to write in the value of each bit and the hexadecimal value for each register. the programmer can photocopy these sheets and reuse them for each application development project. b.2 peripheral addresses figure b-1 is a memory map of the on-chip peripherals showing their addresses in memory. b.3 interrupt addresses table b-1 on page b-5 lists the interrupt starting addresses and sources. b.4 interrupt priorities table b-2 on page b-6 lists the priorities of specific interrupts within interrupt priority levels. b.5 instruction set summary table b-3 on page b-7 summarizes the instruction set. for more detailed information about the instructions, consult the dsp56000 family manual . b.6 programming sheets figure b-2 on page b-14 through figure b-17 on page b-29 are programming sheets for the complete set of programmable registers on the dsp. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-4 dsp56004 user? manual motorola programming reference figure b-1 on-chip peripheral memory map 23 16 15 8 7 0 x:$ffff interrupt priority register (ipr) x:$fffe reserved x:$fffd pll control register (pctl) x:$fffc reserved x:$fffb reserved x:$fffa reserved x:$fff9 reserved x:$fff8 reserved x:$fff7 gpio control/data register (gpior) x:$fff6 emi write offset register (ewor) x:$fff5 reserved x:$fff4 reserved x:$fff3 shi receive fifo/transmit register (hrx/htx) x:$fff2 shi i 2 c slave address register (hsar) x:$fff1 shi host control/status register (hcsr) x:$fff0 shi host clock control register (hckr) x:$ffef emi refresh control register (ercr) x:$ffee emi data register 1 (edrr1/edwr1) x:$ffed emi offset register 1 (eor1) x:$ffec emi base address register 1 (ebar1) x:$ffeb emi control/status register (ecsr) x:$ffea emi data register 0 (edrr0/edwr0) x:$ffe9 emi offset register 0 (eor0) x:$ffe8 emi base address register 0 (ebar0) x:$ffe7 sai tx2 data register (tx2) x:$ffe6 sai tx1 data register (tx1) x:$ffe5 sai tx0 data register (tx0) x:$ffe4 sai tx control/status register (tcs) x:$ffe3 sai rx1 data register (rx1) x:$ffe2 sai rx0 data register (rx0) x:$ffe1 sai rx control/status register (rcs) x:$ffe0 sai baud rate control register (brc) x:$ffdf reserved x:$ffde reserved x:$ffdd reserved x:$ffdc reserved x:$ffdb reserved x:$ffda reserved x:$ffd9 reserved x:$ffd8 reserved x:$ffd7 reserved x:$ffd6 reserved x:$ffd5 reserved x:$ffd4 reserved x:$ffd3 reserved x:$ffc0 reserved = unused and reserved. read as a random number. to ensure future compatibility, do not write to these registers. = unused and reserved. consult the appropriate chapter for information on how to ensure future compatibility. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-5 table b-1 interrupt starting addresses and sources interrupt starting address ipl interrupt source p:$0000 3 hardware reset p:$0002 3 stack error p:$0004 3 trace p:$0006 3 swi p:$0008 0? irqa p:$000a 0? irqb p:$000c reserved p:$000e reserved p:$0010 0? sai left channel transmitter if txil = 0 p:$0012 0? sai right channel transmitter if txil = 0 p:$0014 0? sai transmitter exception if txil = 0 p:$0016 0? sai left channel receiver if rxil = 0 p:$0018 0? sai right channel receiver if rxil = 0 p:$001a 0? sai receiver exception if rxil = 0 p:$001c reserved p:$001e 3 nmi p:$0020 0? shi transmit data p:$0022 0? shi transmit underrun error p:$0024 0? shi receive fifo not empty p:$0026 reserved p:$0028 0? shi receive fifo full p:$002a 0? shi receive overrun error p:$002c 0? shi bus error p:$002e reserved p:$0030 0? emi write data p:$0032 0? emi read data p:$0034 0? emi ebar0 memory wrap p:$0036 0? emi ebar1 memory wrap p:$0038 reserved p:$003a reserved p:$003c reserved p:$003e 3 illegal instruction p: $0040 0? sai left channel transmitter if txil = 1 p: $0042 0? sai right channel transmitter if txil = 1 p: $0044 0? sai transmitter exception if txil = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-6 dsp56004 user? manual motorola programming reference p: $0046 0? sai left channel receiver if rxil = 1 p: $0048 0? sai right channel receiver if rxil = 1 p: $004a 0? sai receiver exception if rxil = 1 p: $004c reserved :: p: $007e reserved table b-2 interrupt priorities within an ipl priority interrupt level 3 (nonmaskable) highest hardware reset illegal instruction nmi stack error trace lowest swi levels 0, 1, 2 (maskable) highest irqa (external interrupt) irqb (external interrupt) sai receiver exception sai transmitter exception sai left channel receiver sai left channel transmitter sai right channel receiver sai right channel transmitter shi bus error shi receive overrun error shi transmit underrun error shi receive fifo full shi transmit data shi receive fifo not empty emi ebar0 memory wrap emi ebar1 memory wrap emi read data lowest emi write data table b-1 interrupt starting addresses and sources (continued) interrupt starting address ipl interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56004 user? manual b-7 table b-3 instruction set summary (sheet 1 of 7) mnemonic syntax parallel moves instruction program words osc. clock cycles status request bits: sleunzvc abs d (parallel move) 1 + mv 2 + mv * * * * * * * adc s,d (parallel move) 1 + mv 2 + mv * * * * * * * * add s,d (parallel move) 1 + mv 2 + mv * * * * * * * * addl s,d (parallel move) 1 + mv 2 + mv * * * * * * ? * addr s,d (parallel move) 1 + mv 2 + mv * * * * * * * * and s,d (parallel move) 1 + mv 2 + mv * * ? ? 0 and(i) #xx,d 1 2 ? ? ? ? ? ? ? ? asl d (parallel move) 1 + mv 2 + mv * * * * * * ? ? asr d (parallel move) 1 + mv 2 + mv * * * * * * 0 ? bchg #n,x: b-8 dsp56004 user? manual motorola programming reference btst #n,x: programming reference motorola dsp56004 user? manual b-9 jmp xxxx 1 + ea 4 + jx ea jscc xxxx 1 + ea 4 + jx ea jsclr #n,x: b-10 dsp56004 user? manual motorola programming reference ( )s,#n,d ( no parallel move) 1 2 macr ( )s2,s1,d (parallel move) 1 + mv 2 + mv * * * * * * * ( )s1,s2,d (parallel move) ( )s,#n,d ( no parallel move) 1 2 move s,d 1 + mv 2 + mv * * no parallel data move (.....) mv mv immediate short (.....)#xx,d mv mv data move register to register (.....)s,d mv mv * * data move address register update (.....)ea mv mv x memory data move (.....)x: programming reference motorola dsp56004 user? manual b-11 long memory data move (.....)l: b-12 dsp56004 user? manual motorola programming reference move(p) (continued) y: |